74AUP1G125GW - NXP

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

74AUP1G125GW
Manufacturer

NXP
ChipWorker Part#

CW151377986
Category

Logic Controller, Logic IC
Package

TSSOP
Description

NXP 74AUP1G125GW Buffer / Line Driver, 74AUP1G125, 0.8V to 3.6V, TSSOP-5
Documentation

Datasheet

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74AUP1G125GW Specifications

Attribute	Attribute Value

Part Number	74AUP1G125GW
Manufacturer	NXP
ChipWorker Part#	CW151377986
Category	Logic Controller, Logic IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	5 Pin
Case/Package	TSSOP
Supply Voltage (DC)	800mV (min)
Number of Positions	5 Position
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	0.8 V
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Operating Temperature	-40℃ ~ 125℃
Product Lifecycle Status	Unknown
Packaging	Each
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/12/17

Product Description

The 74AUP1G125GW is a single non-inverting Buffer/Line Driver with 3-state output. The 3-state output is controlled by the output enable input (OE). A HIGH level at pin OE causes the output to assume a high-impedance OFF-state. This device has the input-disable feature, which allows floating input signals. The inputs are disabled when the output enable input OE) is HIGH. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 to 3.6V. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 to 3.6V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.
High noise immunity
Input-disable allows floating input conditions
IOFF circuitry provides partial power-down mode operation
Low static power consumption, ICC = 0.9µA maximum
Latch-up performance exceeds 100mA per JESD 78 class II
Inputs accept voltages up to 3.6V
Low noise overshoot and undershoot <10% of VCC

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