74AUP2G14GW - NXP

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

74AUP2G14GW
Manufacturer

NXP
ChipWorker Part#

CW135092745
Category

Logic Control, Logic Gate IC
Package

SOT-363
Description

NXP 74AUP2G14GW Inverter, Schmitt Trigger, 74AUP2G14, 1Input, 4mA, 0.8V to 3.6V, SOT-363-6
Documentation

Datasheet

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74AUP2G14GW Specifications

Attribute	Attribute Value

Part Number	74AUP2G14GW
Manufacturer	NXP
ChipWorker Part#	CW135092745
Category	Logic Control, Logic Gate IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	6 Pin
Case/Package	SOT-363
Supply Voltage (DC)	800mV (min)
Output Current	4 mA
Number of Positions	6 Position
Number of Inputs	1 Input
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	0.8 V
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Operating Temperature	-40℃ ~ 125℃
Product Lifecycle Status	Unknown
Packaging	Cut Tape (CT)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/12/17

Product Description

The 74AUP2G14GW is a low-power dual Schmitt-trigger inverter provides two inverting buffer with Schmitt-trigger action which accept standard input signals. The device is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 to 3.6V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The inputs switch at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT- is defined as the input hysteresis voltage VH.
High noise immunity
ESD Protection - HBM JESD22-A114F >5000V, MM JESD22-A115-A >200V, CDM JESD22-C101E >1000V
0.9µA Low static power consumption (ICC)
Latch-up performance exceeds 100mA per JESD 78 Class II
Inputs accept voltages up to 3.6V
<10% of VCC Low noise overshoot and undershoot
IOFF circuitry provides partial power-down mode operation

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