74HC259D - NXP

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

74HC259D
Manufacturer

NXP
ChipWorker Part#

CW135100007
Category

Latche IC
Package

SOIC
Description

IC HC/UH SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDSO16, 3.9MM, PLASTIC, MS-012, SOT-109, SOP-16, FF/Latch
Documentation

Datasheet

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74HC259D Specifications

Attribute	Attribute Value

Part Number	74HC259D
Manufacturer	NXP
ChipWorker Part#	CW135100007
Category	Latche IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	16 Pin
Case/Package	SOIC
Supply Voltage (DC)	5.00 V, 6.00 V (max)
Output Current	25 mA
Number of Circuits	1 Circuit
Number of Positions	16 Position
Number of Bits	8 Bit
Polarity	Non-Inverting
Number of Gates	1 Gate
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage (Max)	6 V
Supply Voltage (Min)	2 V
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Size-Length	10 mm
Size-Width	4 mm
Size-Height	1.45 mm
Product Lifecycle Status	Unknown
Packaging	Each
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/12/17
ECCN Code	EAR99

Product Description

The 74HC259D is a 8-bit Addressable Latch features four modes of operation. In the addressable latch mode, data on the D input is written into the latch addressed by the inputs AO to A3. The addressed latch will follow the data input, non-addressed latches will retain their previous states. In memory mode, all latches retain their previous states and are unaffected by the data or address inputs. In the 3-to-8 decoding or demultiplexing mode, the addressed output follows the D input and all other outputs are low. In the reset mode, all outputs are forced low and unaffected by the data or address inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
Serial-to-parallel capability
Output from each storage bit available
Random (addressable) data entry
Easily expandable
Common reset input
Useful as a 3-to-8 active high decoder
CMOS Input level
Complies with JEDEC standard No. 7A

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