74HC40103D - NXP

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

74HC40103D
Manufacturer

NXP
ChipWorker Part#

CW160946072
Category

Counter, Counter IC
Package

SOIC
Description

IC HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 8Bit DOWN BINARY COUNTER, PDSO16, 3.9MM, PLASTIC, MS-012, SOT-109-1, SO-16, Counter
Documentation

Datasheet

74HC40103D Global Supplier

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74HC40103D Specifications

Attribute	Attribute Value

Part Number	74HC40103D
Manufacturer	NXP
ChipWorker Part#	CW160946072
Category	Counter, Counter IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	16 Pin
Case/Package	SOIC
Supply Voltage (DC)	2.00V (min)
Number of Positions	16 Position
Clock Speed	35 MHz
Number of Bits	8 Bit
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage (Max)	6 V
Supply Voltage (Min)	2 V
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Product Lifecycle Status	Unknown
Packaging	Each
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/12/17

Product Description

The 74HC40103D is a 8-bit synchronous Down Counter has control inputs for enabling or disabling the clock, for clearing the counter to its maximum count and for presetting the counter either synchronously or asynchronously. In normal operation, the counter is decremented by one count on each positive-going transition of the clock. Counting is inhibited when the terminal enable input (TE\\) is high. The terminal count output (TC\\) goes low when the count reaches zero if TE\ is low and remains low for one full clock period. When the synchronous preset enable input (PE\\) is low, data at the jam input (P0 to P7) is clocked into the counter on the next positive-going clock transition regardless of the state of TE\\. When the asynchronous preset enable input (PL\\) is low, data at the jam input (P0 to P7) is asynchronously forced into the counter regardless of the state of PE\, TE\ or CP. The jam inputs (P0 to P7) represent a single 8-bit binary word.
Cascadable
Synchronous or asynchronous preset
Low-power dissipation
CMOS Input levels
Complies with JEDEC standard No. 7A

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