74HC75D - NXP

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

74HC75D
Manufacturer

NXP
ChipWorker Part#

CW116265731
Category

Latche IC
Package

SOIC
Description

IC HC/UH SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PDSO16, 3.9MM, PLASTIC, MS-012, SOT-109-1, SO-16, FF/Latch
Documentation

Datasheet

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74HC75D Specifications

Attribute	Attribute Value

Part Number	74HC75D
Manufacturer	NXP
ChipWorker Part#	CW116265731
Category	Latche IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	16 Pin
Case/Package	SOIC
Supply Voltage (DC)	2.00V (min)
Output Current	5.2 mA
Number of Circuits	4 Circuit
Number of Positions	16 Position
Number of Bits	4 Bit
Number of Gates	4 Gate
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage (Max)	6 V
Supply Voltage (Min)	2 V
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Size-Length	10 mm
Size-Width	4 mm
Size-Height	1.45 mm
Product Lifecycle Status	Unknown
Packaging	Each
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/12/17

Product Description

The 74HC75D is a quad bistable Transparent Latch with complementary outputs. Two latches are simultaneously controlled by one of two active high enable inputs (LE12 and LE34). When LEnn is high, the data enters the latches and appears at the nQ outputs. The nQ outputs follow the data inputs (nD) as long as LEnn is high (transparent). The data on the nD inputs one set-up time prior to the high-to-low transition of the LEnn will be stored in the latches. The latched outputs remain stable as long as the LEnn is low. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
Complementary Q and Q\ outputs
VCC and GND on the center pins
Low-power dissipation
CMOS Input level
Complies with JEDEC standard No. 7A

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