74HCT4046AD - NXP

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

74HCT4046AD
Manufacturer

NXP
ChipWorker Part#

CW142834551
Category

Phase Locked Loop, PLL IC
Package

SOIC
Description

PLL Single Up to 17MHz 16Pin SO PLL Single Up to 17MHz 16Pin SO
Documentation

Datasheet

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74HCT4046AD Specifications

Attribute	Attribute Value

Part Number	74HCT4046AD
Manufacturer	NXP
ChipWorker Part#	CW142834551
Category	Phase Locked Loop, PLL IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	16 Pin
Case/Package	SOIC
Frequency	21 MHz
Supply Voltage (DC)	5.00 V, 5.50 V (max)
Supply Current	50 mA
Number of Positions	16 Position
Number of Gates	1 Gate
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	4.5 V
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Size-Length	10 mm
Size-Width	4 mm
Size-Height	1.45 mm
Product Lifecycle Status	Unknown
Packaging	Each
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/12/17

Product Description

The 74HCT4046AD is a high-speed Si-gate CMOS Device and are pin compatible with the "4046" of the "4000B" series. They are specified in compliance with JEDEC standard no. 7A. The 74HCT4046A is phase-locked-loop circuits that comprise a linear voltage-controlled oscillator (VCO) and three different phase comparators (PC1, PC2 and PC3) with a common signal input amplifier and a common comparator input. The signal input can be directly coupled to large voltage signals or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive low-pass filter, the "4046A" forms a second-order loop PLL. The excellent VCO linearity is achieved by the use of linear op-amp techniques. The VCO requires one external capacitor C1 (between C1A and C1B) and one external resistor R1 (between R1 and GND) or two external resistors R1 and R2 (between R1 and GND and R2 and GND).
Low power consumption
Excellent VCO frequency linearity
VCO-inhibit control for ON/OFF keying and for low standby power consumption
Minimal frequency drift
Zero voltage offset due to op-amp buffering

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