74LCX373MTCX - Fairchild

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

74LCX373MTCX
Manufacturer

Fairchild
ChipWorker Part#

CW36210578
Category

Latche IC
Package

TSSOP-20
Description

Latch Transparent 3-ST 8CH D-Type 20Pin TSSOP T/R
Documentation

Datasheet

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74LCX373MTCX Specifications

Attribute	Attribute Value

Part Number	74LCX373MTCX
Manufacturer	Fairchild
ChipWorker Part#	CW36210578
Category	Latche IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	20 Pin
Case/Package	TSSOP-20
Supply Voltage (DC)	2.00V (min)
Number of Circuits	8 Circuit
Number of Channels	8 Channel
Number of Positions	20 Position
Number of Bits	8 Bit
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	2V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	2 V
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Size-Length	6.5 mm
Size-Width	4.4 mm
Size-Height	0.9 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The 74LCX373MTCX is an Octal Transparent D Latch with 3-state outputs for bus organized system applications. The device is designed for low voltage applications with capability of interfacing to a 5V signal environment. The LCX373 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE standard outputs are controlled by the Output Enable (OE\\) input. When OE\ is LOW, the standard outputs are in the 2-state mode. When OE\ is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches.
Power down high impedance inputs and outputs
Supports live insertion/withdrawal
±24mA Output drive
Implements proprietary noise/EMI reduction circuitry
Latch-up performance exceeds JEDEC 78 conditions

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