74LVC1G175GV - NXP

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

74LVC1G175GV
Manufacturer

NXP
ChipWorker Part#

CW764880279
RoHS

Lead free / RoHS Compliant
Description

Single D-type flip-flop with reset; positive-edge trigger
Documentation

Datasheet

74LVC1G175GV Global Supplier

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74LVC1G175GV Specifications

Attribute	Attribute Value

Part Number	74LVC1G175GV
Manufacturer	NXP
ChipWorker Part#	CW764880279
Documentation	Datasheet
Case/Package	TSSOP
	expand all
Product Lifecycle Status	Unknown
RoHS	RoHS Compliant

Product Description

General description
The 74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output.
The master reset (MR) is an asynchronous active LOW input and operates independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.
The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times.
Features
■ Wide supply voltage range from 1.65 V to 5.5 V
■ 5 V tolerant inputs for interfacing with 5 V logic
■ High noise immunity
■ Complies with JEDEC standard:
◆ JESD8-7 (1.65 V to 1.95 V)
◆ JESD8-5 (2.3 V to 2.7 V)
◆ JESD8B/JESD36 (2.7 V to 3.6 V).
■ ±24 mA output drive (VCC = 3.0 V)
■ ESD protection:
◆ HBM JESD22-A114E exceeds 2000 V
◆ MM JESD22-A115-A exceeds 200 V.
■ CMOS low power consumption
■ Latch-up performance exceeds 250 mA
■ Direct interface with TTL levels
■ Inputs accept voltages up to 5 V
■ Multiple package options
■ Specified from −40 °C to +85 °C and −40 °C to +125 °C.

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