74LVC1G74DP - NXP

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

74LVC1G74DP
Manufacturer

NXP
ChipWorker Part#

CW160930882
Category

Active Chip
Package

SOT-505-2
Description

IC LVC/LCX/Z SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO8, 3MM WIDTH, 0.5MM LENGTH, PLASTIC, SOT505-2, TSSOP-8, FF/Latch
Documentation

Datasheet

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74LVC1G74DP Specifications

Attribute	Attribute Value

Part Number	74LVC1G74DP
Manufacturer	NXP
ChipWorker Part#	CW160930882
Category	Active Chip
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	8 Pin
Case/Package	SOT-505-2
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-40 ℃
	expand all
Size-Length	3.1 mm
Size-Width	3.1 mm
Size-Height	0.95 mm
Product Lifecycle Status	Unknown
RoHS	RoHS Compliant
Lead-Free Status	Lead Free

Product Description

General description
The 74LVC1G74 is a single positive edge triggered D-type flip-flop with individual data (D)
inputs, clock (CP) inputs, set (SD) and reset (RD) inputs, and complementary Q and Q
outputs.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing damaging backflow current through the device when it is powered down.
The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.
Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and
fall times.
Features and benefits
 Wide supply voltage range from 1.65 V to 5.5 V
 5 V tolerant inputs for interfacing with 5 V logic
 High noise immunity
 Complies with JEDEC standard:
 JESD8-7 (1.65 V to 1.95 V)
 JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
 ESD protection:
HBM JESD22-A114F exceeds 2000 V
 MM JESD22-A115-A exceeds 200 V
±24 mA output drive (VCC=3.0V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
Specified from -40F℃ to +85℃ and 40℃ to +125℃

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