74LVC1T45GW - NXP

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

74LVC1T45GW
Manufacturer

NXP
ChipWorker Part#

CW56389807
Category

Logic Controller, Logic IC
Package

SOT-363
Description

NXP 74LVC1T45GW Transceiver, 74LVC145, 1.2V to 5.5V, SOT-363-6
Documentation

Datasheet

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74LVC1T45GW Specifications

Attribute	Attribute Value

Part Number	74LVC1T45GW
Manufacturer	NXP
ChipWorker Part#	CW56389807
Category	Logic Controller, Logic IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	6 Pin
Case/Package	SOT-363
Supply Voltage (DC)	1.20V (min)
Number of Positions	6 Position
Data Rate	420 Mbps
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	1.2 V
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Size-Length	2.2 mm
Size-Width	1.35 mm
Size-Height	1 mm
Operating Temperature	-40℃ ~ 125℃
Product Lifecycle Status	Unknown
Packaging	Cut Tape (CT)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/12/17
HK STC License	NLR

Product Description

The 74LVC1T45GW is a dual supply Translating Transceiver with 3-state outputs that enable bidirectional level translation. It features two 1-bit input-output ports, a direction control input (DIR) and dual supply pins. Both VCC(A) and VCC(B) can be supplied at any voltage between 1.2 and 5.5V making the device suitable for translating between any of the low voltage nodes. Pins A and DIR are referenced to VCC(A) and pin B is referenced to VCC(B). A HIGH on DIR allows transmission from A to B and a LOW on DIR allows transmission from B to A. The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both A port and B port are in the high-impedance OFF-state. Active bus hold circuitry in the 74LVCH1T45 holds unused or floating data inputs at a valid logic level.
High noise immunity
IOFF circuitry provides partial Power-down mode operation
Complies with JEDEC standards
Suspend mode
16µA Maximum ICC low power consumption
Inputs accept voltages up to 5.5V
Latch-up performance exceeds 100mA per JESD 78 class II
±24mA Output drive

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