AD1937WBSTZ - ADI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

AD1937WBSTZ
Manufacturer

ADI
ChipWorker Part#

CW1933511
Category

CODEC
Package

LQFP-64
Description

Audio Codec 4ADC / 8DAC 24Bit 64Pin LQFP
Documentation

Datasheet

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AD1937WBSTZ Specifications

Attribute	Attribute Value

Part Number	AD1937WBSTZ
Manufacturer	ADI
ChipWorker Part#	CW1933511
Category	CODEC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	64 Pin
Case/Package	LQFP-64
Number of Channels	12 Channel
Number of Positions	64 Position
Power Dissipation	429 mW
Sample Rate	192 KSPS
Resolution (Bits)	24.0 Bit
Number of ADCs	4 ADC
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-40 ℃
Power Dissipation (Max)	429 mW
Number of Input Channels	4 Channel
Number of Output Channels	8 Channel
Number of DACs	8 DAC
Supply Voltage	3V ~ 3.6V
	expand all
Size-Length	10.2 mm
Size-Width	10.2 mm
Size-Height	1.45 mm
Operating Temperature	-40℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Cut Tape (CT)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/12/17
ECCN Code	EAR99

Product Description

The AD1937WBSTZ is a 24-bit high-performance Single-chip Codec provides four analog-to-digital converters (ADCs) with differential input and eight digital-to-analog converters (DACs) with differential output, using the patented multibit sigma delta (Σ-Δ) architecture. An I²C® port is included, allowing a microcontroller to adjust volume and many other parameters. The AD1937 operates from 3.3V digital and analog supplies. It is designed for low EMI. This consideration is apparent in both the system and circuit design architectures. By using the on-board PLL to derive the master clock from the LR (frame) clock or from an external crystal, it eliminates the need for a separate high frequency master clock and can also be used with a suppressed bit clock. The DACs and ADCs are designed using the latest Analog Devices continuous time architecture to further minimize EMI. By using 3.3V supplies, power consumption is minimized and further reduces emissions.
PLL generated clock or direct master clock
Low EMI design
Differential ADC input
Differential DAC output
Log volume control with auto ramp function
I²C Controllable for flexibility
Software-controllable clickless mute
Software power-down

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