AD1938YSTZ - ADI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

AD1938YSTZ
Manufacturer

ADI
ChipWorker Part#

CW25910053
Category

CODEC
Package

LQFP-48
Description

Audio Codec 4ADC / 8DAC 24Bit 48Pin LQFP
Documentation

Datasheet

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AD1938YSTZ Specifications

Attribute	Attribute Value

Part Number	AD1938YSTZ
Manufacturer	ADI
ChipWorker Part#	CW25910053
Category	CODEC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	48 Pin
Case/Package	LQFP-48
Frequency	192 kHz
Supply Voltage (DC)	3.30 V
Number of Positions	48 Position
Number of Bits	24 Bit
Power Dissipation	429 mW
Sample Rate	192 KSPS
Quiescent Current	56.0 mA
Resolution (Bits)	24.0 Bit
Number of ADCs	4 ADC
Operating Temperature (Max)	105 ℃
Operating Temperature (Min)	-40 ℃
Power Dissipation (Max)	429 mW
Number of Input Channels	4 Channel
Number of Output Channels	8 Channel
Number of DACs	8 DAC
Supply Voltage	3V ~ 3.6V
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Size-Length	7 mm
Size-Width	7 mm
Size-Height	1.4 mm
Operating Temperature	-40℃ ~ 105℃
Product Lifecycle Status	Active
Packaging	Each
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/12/17
ECCN Code	EAR99
HK STC License	NLR

Product Description

The AD1938YSTZ is a 24-bit high-performance Single-chip Codec provides four analog-to-digital converters (ADCs) with input and eight digital-to-analog converters (DACs) with single-ended output using the Analog Devices, Inc., patented multibit sigma-delta (Σ-Δ) architecture. An SPI port is included, allowing a microcontroller to adjust volume and many other parameters. The AD1938 operates from 3.3V digital and analog supplies. The AD1938 is designed for low EMI. This consideration is apparent in both the system and circuit design architectures. By using the on-board PLL to derive the master clock from the LR clock or from an external crystal, it eliminates the need for a separate high frequency master clock and can also be used with a suppressed bit clock. The DACs and ADCs are designed using the latest Analog Devices continuous time architectures to further minimize EMI. By using 3.3V supplies, power consumption is minimized, further reducing emissions.
PLL generated clock or direct master clock
Low EMI design
Differential ADC input
Single-ended DAC output
Log volume control with auto ramp function
SPI controllable for flexibility
Software-controllable clickless mute
Software power-down

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- Anti-static packaging
- Anti-vibration foam
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- Electrical testing
- Surface testing

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