AD1974YSTZ - ADI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

AD1974YSTZ
Manufacturer

ADI
ChipWorker Part#

CW377054
Category

Analog to Digital, ADC IC
Package

LQFP-48
Description

ANALOG DEVICES AD1974YSTZ Analog to Digital Converter, 24Bit, 192KSPS, Single, 3V, 3.6V, LQFP
Documentation

Datasheet

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AD1974YSTZ Specifications

Attribute	Attribute Value

Part Number	AD1974YSTZ
Manufacturer	ADI
ChipWorker Part#	CW377054
Category	Analog to Digital, ADC IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	48 Pin
Case/Package	LQFP-48
Supply Voltage (DC)	3.00V (min)
Supply Current	74.0 mA
Number of Circuits	4 Circuit
Number of Channels	4 Channel
Number of Positions	48 Position
Number of Bits	24 Bit
Power Dissipation	429 mW
Sample Rate	192 ksps
Power Consumption	429 mW
Resolution (Bits)	24.0 Bit
Number of ADCs	4 ADC
Operating Temperature (Max)	105 ℃
Operating Temperature (Min)	-40 ℃
Number of Input Channels	4 Channel
Supply Voltage	3V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	3 V
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Size-Length	7 mm
Size-Width	7 mm
Size-Height	1.4 mm
Operating Temperature	-40℃ ~ 105℃
Product Lifecycle Status	Active
Packaging	Tray
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/12/17

Product Description

The AD1974YSTZ is a high performance, single-chip four Analog-to-digital Converter (ADC) with differential inputs. An SPI port is included, allowing a microcontroller to enable mutes and adjust many other parameters. The AD1974 operates from 3.3V digital and analog supplies. It is designed for low EMI. This consideration is apparent in both the system and circuit design architectures. By using the on-board phase-locked loop (PLL) to derive the master clock from the LR clock or from an external crystal, the AD1974 eliminates the need for a separate high frequency master clock and can also be used with a suppressed bit clock. The ADC is designed using the latest continuous time architectures from analog devices to further minimize EMI. By using 3.3V supplies, power consumption is minimized, further reducing emissions.
Phase-locked loop generated or direct master clock
Tolerance for 5V logic inputs
Differential ADC input
SPI™ controllable for flexibility
Software-controllable clickless mute
Software power-down
Right justified, left justified, I²S and TDM modes
Master and slave modes up to 16-channel input/output

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