AD7782BRUZ - ADI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

AD7782BRUZ
Manufacturer

ADI
ChipWorker Part#

CW2901526
Category

Analog to Digital, ADC IC
Package

TSSOP-16
Description

Analogue to Digital Converter, 24Bit, 19.79 SPS, Single, 2.7V, 3.6V, TSSOP
Documentation

Datasheet

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AD7782BRUZ Specifications

Attribute	Attribute Value

Part Number	AD7782BRUZ
Manufacturer	ADI
ChipWorker Part#	CW2901526
Category	Analog to Digital, ADC IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	16 Pin
Case/Package	TSSOP-16
Supply Voltage (DC)	2.70V (min)
Supply Current	1.50 mA
Number of Circuits	1 Circuit
Number of Channels	2 Channel
Number of Positions	16 Position
Number of Bits	24 Bit
Power Dissipation	3.9 mW
Sample Rate	19.79 SPS
Power Consumption	3.9 mW
Resolution (Bits)	24.0 Bit
Input Impedance	2.50 MΩ
Number of ADCs	1 ADC
Number of Inputs	2 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Number of Input Channels	2 Channel
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	2.7 V
	expand all
Size-Length	5 mm
Size-Width	4.4 mm
Size-Height	1.05 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Each
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
Mil-Spec	No
ECCN Code	EAR99

Product Description

The AD7782BRUZ is a read only pin configured sigma-delta Analog-to-digital Converter (ADC) for low-frequency measurement applications. The 24-bit sigma-delta ADC contains two fully differential analog input channels that can be configured with a gain of 1 or 16 allowing full-scale input signal ranges of ±2.56V or ±160mV from a 2.5V differential reference input. It has an extremely simple, read-only digital interface which can be operated in master mode or slave mode. There are no on-chip registers to be programmed. The input signal range and input channel selection are configured using two external pins. The device operates from a 32.768kHz crystal with an on-chip PLL generating the required internal operating frequency. The output data rate from the part is fixed via the master clock at 19.79Hz and provides simultaneous 50 and 60Hz rejection at this update rate. 18-bit p-p resolution can be obtained at this update rate.
Pin configurable
Pin selectable input channels
Pin programmable input ranges
Master or slave mode of operation
3-wire serial SPI™/QSPI™/MICROWIRE™/DSP compatible Schmitt trigger on SCLK
Rail-rail input buffer and PGA

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