AD9122BCPZRL - ADI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

AD9122BCPZRL
Manufacturer

ADI
ChipWorker Part#

CW647965
Category

Digital to Analog, DAC IC
Package

LFCSP-72
Description

DAC 2CH Current Steering 16Bit 72Pin LFCSP EP T/R
Documentation

Datasheet

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AD9122BCPZRL Specifications

Attribute	Attribute Value

Part Number	AD9122BCPZRL
Manufacturer	ADI
ChipWorker Part#	CW647965
Category	Digital to Analog, DAC IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	72 Pin
Case/Package	LFCSP-72
Number of Outputs	2 Output
Number of Channels	2 Channel
Number of Bits	16 Bit
Power Dissipation	1.10 W
Resolution (Bits)	16.0 Bit
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Number of DACs	2 DAC
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Size-Height	0.83 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
Mil-Spec	No

Product Description

**GENERAL DESCRIPTION**
The AD9122 is a dual 16-bit, high dynamic range, digital-to analog converter (DAC) that provides a sample rate of 1200 MSPS, permitting a multicarrier generation up to the Nyquist frequency. It includes features optimized for direct conversion transmit applications, including complex digital modulation, and gain and offset compensation. The DAC outputs are optimized to interface seamlessly with analog quadrature modulators, such as the ADL537x F-MOD series from Analog Devices, Inc. A 4-wire serial port interface provides for programming/readback of many internal parameters. Full-scale output current can be programmed over a range of 8.7 mA to 31.7 mA. The AD9122 comes in a 72-lead LFCSP.
**FEATURES**
**Flexible LVDS interface allows word, byte, or nibble load**
**Single-carrier W-CDMA ACLR = 82 dBc @ 122.88 MHz IF**
**Analog output: adjustable 8.7 mA to 31.7 mA, R****L ****= 25 Ω to 50 Ω**
**Novel 2×/4×/8× interpolator/complex modulator allows ****carrier placement anywhere in the DAC bandwidth**
**Digital gain and phase adjustment for sideband suppression**
**Multiple chip synchronization interfaces**
**High performance, low noise PLL clock multiplier**
**Digital inverse sinc filter**
**Flexible LVDS interface allows word, byte, or nibble load**
**Low power: 1.5 W @ 1.2 GSPS, 800 mW @ 500 MSPS, full ****operating conditions**
**72-lead, exposed paddle LFCSP**

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