AD9142 - ADI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

AD9142
Manufacturer

ADI
ChipWorker Part#

CW380621204
Description

Dual, 16Bit, 1600MSPS, TxDAC+ Digital-to-Analog Converter
Documentation

Datasheet

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Product Description

Product Details
The AD9142 is a dual, 16-bit, high dynamic range digital-to-analog converter (DAC) that provides a sample rate of 1600 MSPS, permitting a multicarrier generation up to the Nyquist frequency. The AD9142 TxDAC+® includes features optimized for direct conversion transmit applications, including complex digital mod-ulation, input signal power detection, and gain, phase, and offset compensation. The DAC outputs are optimized to interface seamlessly with analog quadrature modulators, such as the ADL537x F-MOD series and the ADRF670x series from Analog Devices, Inc. A 3-wire serial port interface provides for the pro-gramming/readback of many internal parameters. Full-scale output current can be programmed over a range of 9 mA to 33 mA. The AD9142 is available in a 72-lead LFCSP.*PRODUCT HIGHLIGHTS**
1. Advanced low spurious and distortion design techniques provide high quality synthesis of wideband signals from baseband to high intermediate frequencies.
2. Very small inherent latency variation simplifies both software and hardware design in the system. It allows easy multichip synchronization for most applications.
3. New low power architecture improves power efficiency (mW/MHz/channel) by 30%.
4. Input signal power and FIFO error detection simplify designs for downstream analog circuitry protection.
5. Programmable transmit enable function allows easy design balance between power consumption and wakeup time.
**
APPLICATIONS*
Wireless communications: 3G/4G and MC-GSM base stations,
wideband repeaters, software defined radios
Wideband communications: point-to-point, LMDS/MMDS
Transmit diversity/MIMO
Instrumentation
Automated test equipment
### Features and Benefits
Very small inherent latency variation: <2 DAC clock cycles
Proprietary low spurious and distortion design
6-carrier GSM ACLR = 79 dBc at 200 MHz IF
SFDR > 85 dBc (bandwidth = 300 MHz) at ZIF
Flexible 16-bit LVDS interface
Supports word and byte load
Multiple chip synchronization
Fixed latency and data generator latency compensation
Selectable 2×, 4×, 8× interpolation filter
Low power architecture
fS/4 power saving coarse mixer
Input signal power detection
Emergency stop for downstream analog circuitry protection
FIFO error detection
See data sheet for additional features

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