AD9510BCPZ - ADI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

AD9510BCPZ
Manufacturer

ADI
ChipWorker Part#

CW644412
Category

Clock Buffer, Driver, PLL IC
Package

LFCSP-64
Description

Clock Generator 0MHz to 1.6GHz Input 1200MHz Output 64Pin LFCSP EP
Documentation

Datasheet

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AD9510BCPZ Specifications

Attribute	Attribute Value

Part Number	AD9510BCPZ
Manufacturer	ADI
ChipWorker Part#	CW644412
Category	Clock Buffer, Driver, PLL IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	64 Pin
Case/Package	LFCSP-64
Frequency	1.2 GHz
Supply Voltage (DC)	3.13V (min)
Number of Outputs	8 Output
Number of Circuits	1 Circuit
Number of Positions	64 Position
Clock Speed	800 MHz
Power Dissipation	1.5 W
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Power Dissipation (Max)	1500 mW
Supply Voltage	3.135V ~ 3.465V
Supply Voltage (Max)	3.465 V
Supply Voltage (Min)	3.135 V
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Size-Length	9 mm
Size-Width	9 mm
Size-Height	0.83 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tray
RoHS	RoHS Compliant
Lead-Free Status	PB free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2013/06/20
ECCN Code	EAR99
HK STC License	NLR

Product Description

The AD9510BCPZ is a 8-output Clock Distribution IC provides a multi-output clock distribution function along with an on-chip phase-locked loop (PLL) core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this device. By connecting an external voltage-controlled crystal oscillator (VCXO) or voltage-controlled oscillator (VCO) to the CLK2 and CLK2B pins, frequencies of up to 1.6GHz can be synchronized to the input reference. Four outputs are low voltage positive emitter-coupled logic (LVPECL) at 1.2GHz and four are selectable as either LVDS (800MHz) or CMOS (250MHz) levels. Each output has a programmable divider that can be bypassed or set to divide by any integer up to 32. The phase of one clock output relative to another clock output can be varied by means of a divider phase select function that serves as a coarse timing adjustment.
Low phase noise phase-locked loop core
Reference input frequencies to 250MHz
Programmable dual modulus pre-scalar
Programmable charge pump (CP) current
Separate CP supply (VCPS) extends tuning range
Phase select for output-to-output coarse delay adjust
Complementary metal oxide conductor (CMOS) clock outputs
Serial control port

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