AD9512BCPZ - ADI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

AD9512BCPZ
Manufacturer

ADI
ChipWorker Part#

CW224145
Category

Clock Buffer, Driver, PLL IC
Package

LFCSP-48
Description

Clock Generator 0MHz to 1.6GHz Input 1200MHz Output 48Pin LFCSP EP
Documentation

Datasheet

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AD9512BCPZ Specifications

Attribute	Attribute Value

Part Number	AD9512BCPZ
Manufacturer	ADI
ChipWorker Part#	CW224145
Category	Clock Buffer, Driver, PLL IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	48 Pin
Case/Package	LFCSP-48
Frequency	1.2 GHz
Supply Voltage (DC)	3.13V (min)
Number of Outputs	5 Output
Number of Circuits	1 Circuit
Number of Positions	48 Position
Clock Speed	800 MHz
Power Dissipation	0.85 W
Number of Inputs	1 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	3.135V ~ 3.465V
Supply Voltage (Max)	3.465 V
Supply Voltage (Min)	3.135 V
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Size-Length	7 mm
Size-Width	7 mm
Size-Height	0.83 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tray
RoHS	RoHS Compliant
Lead-Free Status	Contains Lead
REACH SVHC Compliance	No SVHC
ECCN Code	EAR99

Product Description

The AD9512BCPZ is a 5-output Clock Distribution IC provides multi-output clock distribution in a design that emphasizes low jitter and low phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements can also benefit from this part. There are five independent clock outputs. Three outputs are LVPECL (1.2GHz) and two are selectable as either LVDS (800MHz) or CMOS (250MHz) levels. Each output has a programmable divider that may be bypassed or set to divide by any integer up to 32. The phase of one clock output relative to another clock output may be varied by means of a divider phase select function that serves as a coarse timing adjustment. One of the LVDS/CMOS outputs features a programmable delay element with a range of up to 10ns of delay. This fine tuning delay block has 5-bit resolution, giving 32 possible delays from which to choose.
Phase select for output-to-output coarse delay adjust
Serial control port
Two 1.6GHz, differential clock inputs
5 Programmable dividers, 1 to 32, all integers
3 Independent 1.2GHz LVPECL outputs
Fine delay adjust on 1 LVDS/CMOS output
ESD sensitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection.

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