AD9523 - ADI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

AD9523
Manufacturer

ADI
ChipWorker Part#

CW983488663
Description

Low Jitter Clock Generator With 14 Lvpecl/lvds/hstl/29 Lvcmos Outputs Ad9523
Documentation

Datasheet

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Product Description

Product Details
The AD9523 provides a low power, multi-output, clock distribution function with low jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 3.6 GHz to 4.0 GHz.
The AD9523 is designed to support the clock requirements for long term evolution (LTE) and multicarrier GSM base station designs. It relies on an external VCXO to provide the reference jitter cleanup to achieve the restrictive low phase noise requirements necessary for acceptable data converter SNR performance.
The input receivers, oscillator, and zero delay receiver provide both single-ended and differential operation. When connected to a recovered system reference clock and a VCXO, the device generates 14 low noise outputs with a range of 1 MHz to 1 GHz, and one dedicated buffered output from the input PLL (PLL1). The frequency and phase of one clock output relative to another clock output can be varied by means of a divider phase select function that serves as a jitter-free coarse timing adjustment in increments that are equal to the period of the signal coming out of the VCO.
An in-package EEPROM can be programmed through the serial interface to store user-defined register settings for power-up and chip reset.
**Applications**
LTE and multicarrier GSM base stations
Wireless and broadband infrastructure
Medical instrumentation
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
Low jitter, low phase noise clock distribution
Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols
Forward error correction (G.710)
High performance wireless transceivers
ATE and high performance instrumentation
### Features and Benefits
Output frequency: <1 MHz to 1 GHz
Start-up frequency accuracy: <±100 ppm (determined by VCXO reference accuracy)
Zero delay operation
Input-to-output edge timing: <±500 ps
14 outputs: configurable LVPECL, LVDS, HSTL, and LVCMOS
14 dedicated output dividers with jitterless adjustable delay
Adjustable delay: 8 resolution steps of ½ period of VCO output divider
Output-to-output skew: <±50 ps
Duty-cycle correction for odd divider settings
Automatic synchronization of all outputs on power-up
Nonvolatile EEPROM stores configuration settings
Please see data sheet for additional features

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