AD9528BCPZ - ADI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

AD9528BCPZ
Manufacturer

ADI
ChipWorker Part#

CW213055
Category

Clock Generator IC
Package

LFCSP-72
Description

PLL Clock Generator Dual 3450MHz to 4025MHz 72Pin LFCSP Tray
Documentation

Datasheet

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AD9528BCPZ Specifications

Attribute	Attribute Value

Part Number	AD9528BCPZ
Manufacturer	ADI
ChipWorker Part#	CW213055
Category	Clock Generator IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	72 Pin
Case/Package	LFCSP-72
Frequency	1.25 GHz
Supply Voltage (DC)	3.13V (min)
Number of Outputs	14 Output
Number of Circuits	1 Circuit
Number of Positions	72 Position
Power Dissipation	1.81 W
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Power Dissipation (Max)	1810 mW
Supply Voltage	3.135V ~ 3.465V
Supply Voltage (Max)	3.465 V
Supply Voltage (Min)	3.135 V
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Size-Length	10.1 mm
Size-Width	10.1 mm
Size-Height	0.95 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tray
RoHS	RoHS Compliant
Lead-Free Status	Contains Lead
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/12/17
ECCN Code	EAR99

Product Description

The AD9528BCPZ is a 14-output LVDS/HSTL Clock Generator for use with LTE and multicarrier GSM base stations. The first stage phase-locked loop (PLL) (PLL1) provides input reference conditioning by reducing the jitter present on a system clock. The second stage PLL (PLL2) provides high frequency clocks that achieve low integrated jitter as well as low broadband noise from the clock output drivers. The external VCXO provides the low noise reference required by PLL2 to achieve the restrictive phase noise and jitter requirements necessary to achieve acceptable performance. The integrated SYSREF generator outputs single shot, N-shot or continuous signals synchronous to the PLL1 and PLL2 outputs to time align multiple devices. Each of the 14 output channels contains a divider with coarse digital phase adjustment and an analogue fine phase delay block that allows complete flexibility in timing alignment across all 14 outputs.
Dependent on the voltage controlled crystal oscillator (VCXO) frequency accuracy
Dedicated 8-bit dividers on each output
20ps Typical output to output skew
Duty cycle correction for odd divider settings
Digital frequency lock detect
SPI and I²C-compatible serial control port
Dual PLL architecture
Provides reference input clock clean-up with external VCXO
Redundant reference inputs
Automatic and manual reference switchover modes
Revertive and non-revertive switching
Loss of reference detection with holdover mode
Integrated low-noise VCO

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- Carefully tested and packaged by ChipWorker
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- Anti-static packaging
- Anti-vibration foam
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