AD9548BCPZ - ADI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

AD9548BCPZ
Manufacturer

ADI
ChipWorker Part#

CW1168726
Category

Clock Chip, Timing IC
Package

LFCSP-88
Description

Clock Generator 0.001MHz to 750MHz-IN 450MHz-OUT 88Pin LFCSP EP Tray
Documentation

Datasheet

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AD9548BCPZ Specifications

Attribute	Attribute Value

Part Number	AD9548BCPZ
Manufacturer	ADI
ChipWorker Part#	CW1168726
Category	Clock Chip, Timing IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	88 Pin
Case/Package	LFCSP-88
Frequency	1 GHz
Supply Voltage (DC)	1.71V (min)
Number of Outputs	4 Output
Supply Current	190 mA
Number of Circuits	1 Circuit
Input Current	24.0 mA
Duty Cycle	55% (Max)
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	1.71V ~ 3.465V
Supply Voltage (Max)	1.89 V
Supply Voltage (Min)	1.71 V
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Size-Length	12.1 mm
Size-Width	12.1 mm
Size-Height	0.85 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tray
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance Edition	2015/12/17
ECCN Code	EAR99

Product Description

Product Details
The AD9548 provides synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9548 generates an output clock synchronized to one of up to four differential or eight single-ended external input references. The digital PLL allows for reduction of input time jitter or phase noise associated with the external references. The AD9548 continuously generates a clean (low jitter), valid output clock even when all references have failed by means of a digitally controlled loop and holdover circuitry.
The AD9548 operates over an industrial temperature range of −40°C to +85°C.
**Applications**
Network synchronization
Cleanup of reference clock jitter
GPS 1 pulse per second synchronization
SONET/SDH clocks up to OC-192, including FEC
Stratum 2 holdover, jitter cleanup, and phase transient control
Stratum 3E and Stratum 3 reference clocks
Wireless base stations, controllers
Cable infrastructure
Data communications
### Features and Benefits
Supports Stratum2 stability in holdover mode
Supports reference switchover with phase build-out
Supports hitless reference switchover
Auto/manual holdover and reference switchover
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4 pairs of reference input pins with each pair configurable as a single differential input or as 2 independent single-ended inputs
Input reference frequencies from 1 Hz to 750 MHz
Reference validation and frequency monitoring (1ppm)
Programmable input reference switchover priority
Please see data sheet for additional features.
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