AD9767ASTZ - ADI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

AD9767ASTZ
Manufacturer

ADI
ChipWorker Part#

CW370963
Category

Digital to Analog, DAC IC
Package

LQFP-48
Description

ANALOG DEVICES AD9767ASTZ Digital to Analogue Converter, 14Bit, 125MSPS, Parallel, 3V to 5.5V, LQFP, 48Pins
Documentation

Datasheet

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AD9767ASTZ Specifications

Attribute	Attribute Value

Part Number	AD9767ASTZ
Manufacturer	ADI
ChipWorker Part#	CW370963
Category	Digital to Analog, DAC IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	48 Pin
Case/Package	LQFP-48
Number of Outputs	2 Output
Supply Current	71.0 mA
Number of Channels	2 Channel
Number of Positions	48 Position
Number of Bits	14 Bit
Power Dissipation	0.45 W
Sample Rate	125 Msps
Resolution (Bits)	14.0 Bit
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Power Dissipation (Max)	450 mW
Number of DACs	2 DAC
Supply Voltage	3V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	3 V
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Size-Length	7 mm
Size-Width	7 mm
Size-Height	1.4 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tray
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
Mil-Spec	No
REACH SVHC Compliance Edition	2015/12/17

Product Description

The AD9767ASTZ is a dual-port high speed 2-channel 14-bit CMOS Digital-to-analog Converter (DAC) integrates two high quality TxDAC+® cores, a voltage reference. The AD9763 offers exceptional AC and DC performance while supporting update rates of up to 125MSPS. The AD9763 has been optimized for processing I and Q data in communications applications. The digital interface consists of two double-buffered latches as well as control logic. Separate write inputs allow data to be written to the two DAC ports independent of one another. Separate clocks control the update rate of the DAC. A mode control pin allows the AD9763 to interface to two separate data ports or to a single interleaved high speed data port. In interleaving mode, the input data stream is demuxed into its original I and Q data and then latched. The I and Q data is then converted by the two DAC and updated at half the input data rate. The GAINCTRL pin allows two modes for setting the full-scale current of the two DACs.
Excellent SFDR to Nyquist at 5MHz output - 75dBc
Excellent gain and offset matching - 0.1%
Fully independent or single-resistor gain control
Dual-port or interleaved data

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