ADAU1361BCPZ - ADI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

ADAU1361BCPZ
Manufacturer

ADI
ChipWorker Part#

CW178235
Category

CODEC
Package

LFCSP-32
Description

Audio Codec 2ADC / 2DAC 24Bit 32Pin LFCSP EP
Documentation

Datasheet

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ADAU1361BCPZ Specifications

Attribute	Attribute Value

Part Number	ADAU1361BCPZ
Manufacturer	ADI
ChipWorker Part#	CW178235
Category	CODEC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	32 Pin
Case/Package	LFCSP-32
Sample Rate	96 KSPS
Resolution (Bits)	24.0 Bit
Number of ADCs	2 ADC
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Number of Input Channels	2 Channel
Number of Output Channels	2 Channel
Number of DACs	2 DAC
Supply Voltage	1.8V ~ 3.6V
Supply Voltage (Max)	3.65 V
Supply Voltage (Min)	1.8 V
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Size-Length	5 mm
Size-Width	5 mm
Size-Height	0.83 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tray
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/12/17
ECCN Code	EAR99

Product Description

Product Details
The ADAU1361 is a low power, stereo audio codec that supports stereo 48 kHz record and playback at 14 mW from a 1.8 V analog supply. The stereo audio ADCs and DACs support sample rates from 8 kHz to 96 kHz as well as a digital volume control. The ADAU1361 is ideal for battery-powered audio and telephony applications.
The record path includes an integrated microphone bias circuit and six inputs. The inputs can be mixed and muxed before the ADC, or they can be configured to bypass the ADC. The ADAU1361 includes a stereo digital microphone input.
The ADAU1361 includes five high power output drivers (two differential and three single-ended), supporting stereo head-phones, an earpiece, or other output transducer. AC-coupled or capless configurations are supported. Individual fine level controls are supported on all analog outputs. The output mixer stage allows for flexible routing of audio.
The serial control bus supports the I2C and SPI protocols. The serial audio bus is programmable for I2S, left-/right-justified, and TDM modes. A programmable PLL supports flexible clock generation for all standard integer rates and fractional master clocks from 8 MHz to 27 MHz.
**Applications**
Smartphones / Multimedia phones
Digital Still Cameras / Digital Video Cameras
Portable Media Players/ Portable Audio Players
Phone accessories products
### Features and Benefits
24-bit stereo audio ADC and DAC: >98 dB SNR
Sampling rates from 8 kHz to 96 kHz
Low power: 7 mW record, 7 mW playback, 48 kHz at 1.8 V
6 analog input pins, configurable for single-ended or differential inputs
Flexible analog input/output mixers
Stereo digital microphone input
Analog outputs: 2 differential stereo, 2 single-ended stereo, 1 mono headphone driver output
See Data Sheet for Additional Information

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