ADCLK846 - ADI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

ADCLK846
Manufacturer

ADI
ChipWorker Part#

CW181927046
RoHS

Lead free / RoHS Compliant
Description

1.8V, 6 LVDS/12 CMOS Outputs Low Power Clock Fanout Buffer
Documentation

Datasheet

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ADCLK846 Specifications

Attribute	Attribute Value

Part Number	ADCLK846
Manufacturer	ADI
ChipWorker Part#	CW181927046
Documentation	Datasheet
	expand all
Product Lifecycle Status	Recommended for New Designs
RoHS	RoHS Compliant

Product Description

CIRCUIT DESCRIPTION
The circuit in Figure 1 was constructed by connecting the respective evaluation boards for the individual products. Connections were made with matched cable lengths. The first of three basic requirements to synchronize multiple AD9910’s is to provide a co-incident reference clock (REF CLK).
The setup uses the AD9520 as the REF CLK source for each AD9910 DDS. The AD9520 runs off an external crystal and the internal PLL. The AD9520 distributes phase aligned 1 GHz REF CLKs (PECL outputs) to all four AD9910 evaluation boards. It also provides a CMOS output clock to the Tektronix DG2020A data pattern generator for the IO_UPDATE.
CIRCUIT FUNCTION AND BENEFITS
Synchronization of multiple DDS devices allows precise digital tuning control of the phase and amplitude across multiple frequency carriers. This type of control is useful in radar applications and quadrature (I/Q) upconversion for side-band suppression.
The circuit in Figure 1 demonstrates how to synchronize four AD9910 1 GSPS, DDS chips using the AD9520 clock generator and the ADCLK846 clock fanout buffer. The result is precise phase alignment between the clock and output signals of four AD9910 devices.

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