ADS41B49IRGZT - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

ADS41B49IRGZT
Manufacturer

TI
ChipWorker Part#

CW40829664
Category

Analog to Digital, ADC IC
Package

VQFN-48
Description

Analog to Digital Converter 14Bit 250MSPS Buffered Low Power ADC Single ADC Pipelined 250MSPS 14Bit Parallel/Serial/LVDS 48Pin VQFN EP T/R
Documentation

Datasheet

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ADS41B49IRGZT Specifications

Attribute	Attribute Value

Part Number	ADS41B49IRGZT
Manufacturer	TI
ChipWorker Part#	CW40829664
Category	Analog to Digital, ADC IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	48 Pin
Case/Package	VQFN-48
Supply Voltage (DC)	1.70V (min)
Supply Current	99.5 mA
Number of Circuits	1 Circuit
Number of Channels	1 Channel
Number of Bits	14 Bit
Power Dissipation	180 mW
Sample Rate	250 Msps
Power Consumption	350 mW
Number of ADCs	1 ADC
Number of Inputs	1 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Number of Input Channels	1 Channel
Supply Voltage (Max)	1.9 V
Supply Voltage (Min)	1.7 V
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Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	3A001A5A4

Product Description

The ADS41B49IRGZT is an Analog-to-digital Converter (ADC) featuring integrated analog input buffers. This is member of the ultralow-power ADS4xxx ADC family, this device use innovative design techniques to achieve high dynamic performance and consume extremely low power. The analog input pins have buffers, with benefits of constant performance and input impedance across a wide frequency range. The devices are well-suited for multi-carrier, wide bandwidth communications applications such as PA linearization. The gain option can be used to improve SFDR performance at lower full-scale input ranges, especially at high input frequencies. The integrated dc offset correction loop can be used to estimate and cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled-down power with no loss in performance. The devices support both double data rate (DDR) low-voltage differential signalling (LVDS) and parallel CMOS digital output interfaces.
Digital gain and offset correction
Integrated high-impedance analog input buffer
Ultralow power
High dynamic performance
Output interface
Double data rate LVDS with programmable swing and strength
Programmable gain for SNR, SFDR trade-OFF
DC offset correction
Supports low input clock amplitude
Green product and no Sb/Br

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