AM5K2E04XABDA4 - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

AM5K2E04XABDA4
Manufacturer

TI
ChipWorker Part#

CW80147832
Category

Microprocessor IC
Package

FCBGA-1089
Description

SOC AM5K2Ex ARM Cortex A15 28nm 1089Pin FCBGA
Documentation

Datasheet

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AM5K2E04XABDA4 Specifications

Attribute	Attribute Value

Part Number	AM5K2E04XABDA4
Manufacturer	TI
ChipWorker Part#	CW80147832
Category	Microprocessor IC
Documentation	Datasheet
Number of Pins	1089 Pin
Case/Package	FCBGA-1089
RAM Memory Size	2048 KB
Number of UARTs	2 UART
Operating Temperature (Max)	100 ℃
Operating Temperature (Min)	-40 ℃
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Operating Temperature	-40℃ ~ 100℃
Product Lifecycle Status	Active
Packaging	Tray
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
ECCN Code	5A002.a.1

Product Description

The AM5K2E0x is a high performance device based on TIs KeyStone II Multicore SoC Architecture, incorporating the most performance-optimized Cortex-A15 processor dual-core or quad-core CorePac that can run at a core speed of up to 1.4 GHz. TIs AM5K2E0x device enables a high performance, power-efficient and easy to use platform for developers of a broad range of applications such as enterprise grade networking end equipment, data center networking, avionics and defense, medical imaging, test and automation.
TIs KeyStone II Architecture provides a programmable platform integrating various subsystems (for example, ARM CorePac (Cortex-A15 Processor Quad Core CorePac), network processing, and uses a queue-based communication system that allows the device resources to operate efficiently and seamlessly. This unique device architecture also includes a TeraNet switch that enables the wide mix of system elements, from programmable cores to high-speed IO, to each operate at maximum efficiency with no blocking or stalling.
The AM5K2E0x KeyStone II device integrates a large amount of on-chip memory. The Cortex-A15 processor cores each have 32KB of L1Data and 32KB of L1 Instruction cache. The up to four Cortex A15 cores in the ARM CorePac share a 4MB L2 Cache. The device also integrates 2MB of Multicore Shared Memory (MSMC) that can be used as a shared L3 SRAM. All L2 and MSMC memories incorporate error detection and error correction. For fast access to external memory, this device includes a 64-bit DDR-3 (72-bit with ECC support) external memory interface (EMIF) running at 1600 MTPS.
The device enables developers to use a variety of development and debugging tools that include GNU GCC, GDB, Open source Linux, Eclipse based debugging environment enabling kernel and user space debugging using a variety of Eclipse plug-ins including TI"s industry leading IDE Code Composer Studio.

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