CD4026BE ,Counter, Counter IC - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Popularity Score

214 points

Part No

CD4026BE
Manufacturer

TI
ChipWorker Part#

CW850740
Category

Counter, Counter IC
Package

DIP-16
Description

TEXAS INSTRUMENTS CD4026BE Decade Counter / Divider, 16MHz, 3V to 18V, DIP-16
Documentation

Datasheet
Ships from

Moscow
Наличие

500 pcs In Stock
Estimated Price

$ 0.43

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CD4026BE Specifications

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Attribute	Attribute Value

Part Number	CD4026BE
Manufacturer	TI
ChipWorker Part#	CW850740
Category	Counter, Counter IC
Documentation	Datasheet
Mounting Style	Through Hole
Number of Pins	16 Pin
Case/Package	DIP-16
Supply Voltage (DC)	15.0 V, 18.0 V (max)
Number of Outputs	7 Output
Number of Positions	16 Position
Clock Speed	16 MHz
Number of Bits	5 Bit
Voltage Nodes	5.00 V, 10.0 V, 15.0 V
Number of Inputs	1 Input
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-55 ℃
Supply Voltage	3V ~ 18V
Supply Voltage (Max)	18 V
Supply Voltage (Min)	3 V
	expand all
Size-Length	19.3 mm
Size-Width	6.35 mm
Size-Height	4.57 mm
Operating Temperature	-55℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

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Product Description

The CD4026BE is a CMOS Decade Counter/Divider with decoded 7-segment display outputs and display enable. The CD4026B consists of a 5-stage Johnson decade counter and an output decoder which converts the Johnson code to a 7-segment decoded output for driving one stage in a numerical display. Inputs common to both types are CLOCK, RESET & CLOCK INHIBIT, common outputs are CARRY OUT and the seven decoded outputs. Additional inputs and outputs for the counter include DISPLAY ENABLE input and DISPLAY ENABLE and UNGATED "C-SEGMENT" outputs. A high RESET signal clears the decade counter to its zero count. The counter is advanced one count at the positive clock signal transition if the CLOCK INHIBIT signal is low. Counter advancement via the clock line is inhibited when the CLOCK INHIBIT signal is high. The CLOCK INHIBIT signal can be used as a negative-edge clock if the clock line is held high. Antilock gating is provided on the JOHNSON counter, thus assuring proper counting sequence.
Easily interfaced with 7-segment display types
Ideal for low-power displays
Display enable output
100% Tested for quiescent current at 20V
Standardized, symmetrical output characteristics
Schmitt-triggered clock inputs

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