CD4035BE - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

CD4035BE
Manufacturer

TI
ChipWorker Part#

CW12176821
Category

Shift Register IC
Package

PDIP-16
Description

TEXAS INSTRUMENTS CD4035BE Shift Register, CD4035, Parallel to Serial, 1Element, 4Bit, DIP, 16Pins
Documentation

Datasheet

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CD4035BE Specifications

Attribute	Attribute Value

Part Number	CD4035BE
Manufacturer	TI
ChipWorker Part#	CW12176821
Category	Shift Register IC
Documentation	Datasheet
Mounting Style	Through Hole
Number of Pins	16 Pin
Case/Package	PDIP-16
Frequency	16.0 MHz
Supply Voltage (DC)	15.0 V, 18.0 V (max)
Number of Outputs	4 Output
Number of Circuits	2 Circuit
Number of Positions	16 Position
Number of Bits	4 Bit
Voltage Nodes	5.00 V, 10.0 V, 15.0 V
Number of Inputs	6 Input
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-55 ℃
Supply Voltage	3V ~ 18V
Supply Voltage (Max)	18 V
Supply Voltage (Min)	3 V
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Size-Length	19.3 mm
Size-Width	6.35 mm
Size-Height	4.57 mm
Operating Temperature	-55℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The CD4035BE is a 4-stage CMOS parallel in/parallel out Shift Register for synchronous parallel inputs to each stage and serial inputs to the first stage via JK\ logic. Register stages 2, 3 and 4 are coupled in a serial D flip-flop configuration when the register is in the serial mode (parallel/serial control low). parallel entry into each register stage is permitted when the parallel/serial control is high. In the parallel or serial mode information is transferred on positive clock transitions. When the TRUE/COMPLEMENT control is high, the true contents of the register are available at the output terminals. When the TRUE/COMPLEMENT control is low, the outputs are the complements of the data in the register. The TRUE/COMPLEMENT control functions asynchronously with respect to the clock signal. JK\ input logic is provided on the first stage serial input to minimize logic requirements particularly in counting and sequence-generation applications.
Synchronous parallel entry on all 4 stages
JK\ Inputs on first stage
Asynchronous true/complement control on all outputs
Static flip-flop operation, master-slave configuration
Buffered inputs and outputs

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