CD74AC138E - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

CD74AC138E
Manufacturer

TI
ChipWorker Part#

CW5494638
Category

Logic Controller, Logic IC
Package

DIP-16
Description

TEXAS INSTRUMENTS CD74AC138E Decoder / Demultiplexer, Inverting, AC Family, 1 Gate, 3Input, 8 Output, 1.5V to 5.5V, DIP-16
Documentation

Datasheet

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CD74AC138E Specifications

Attribute	Attribute Value

Part Number	CD74AC138E
Manufacturer	TI
ChipWorker Part#	CW5494638
Category	Logic Controller, Logic IC
Documentation	Datasheet
Mounting Style	Through Hole
Number of Pins	16 Pin
Case/Package	DIP-16
Supply Voltage (DC)	1.50V (min)
Number of Outputs	8 Output
Number of Circuits	1 Circuit
Number of Positions	16 Position
Number of Bits	8 Bit
Number of Gates	1 Gate
Bandwidth	100 MHz
Number of Inputs	3 Input
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-55 ℃
Supply Voltage	1.5V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	1.5 V
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Operating Temperature	-55℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Each
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
Mil-Spec	Yes
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The CD74AC138E is a 3-to-8 inverting Decoder/Demultiplexer designed for high-performance memory-decoding and data-routing applications that require very short propagation-delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of the decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible. The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.
Speed of bipolar F, AS and S, with significantly reduced power consumption
Designed specifically for high-speed memory decoders and data-transmission systems
Incorporate three enable inputs to simplify cascading and/or data reception
Balanced propagation delays
SCR Latchup-resistant CMOS process and circuit design
±24mA Output drive current

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