CD74ACT74E - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

CD74ACT74E
Manufacturer

TI
ChipWorker Part#

CW5776627
Category

Flip Flop IC
Package

DIP-14
Description

Flip Flop D-Type Pos-Edge 2Element 14Pin PDIP Tube
Documentation

Datasheet

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CD74ACT74E Specifications

Attribute	Attribute Value

Part Number	CD74ACT74E
Manufacturer	TI
ChipWorker Part#	CW5776627
Category	Flip Flop IC
Documentation	Datasheet
Mounting Style	Through Hole
Number of Pins	14 Pin
Case/Package	DIP-14
Frequency	85 MHz
Supply Voltage (DC)	4.50V ~ 5.50V
Number of Outputs	1 Output
Output Current	24 mA
Number of Circuits	2 Circuit
Number of Positions	14 Position
Clock Speed	85 MHz
Number of Bits	2 Bit
Voltage Nodes	5.00 V
Number of Gates	2 Gate
Input Capacitance	10 pF
Number of Inputs	1 Input
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-55 ℃
Supply Voltage	4.5V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	4.5 V
	expand all
Size-Length	19.3 mm
Size-Width	6.35 mm
Size-Height	4.57 mm
Operating Temperature	-55℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

description/ordering information
The ’ACT74 dual positive-edge-triggered devices are D-type flip-flops.
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
• Inputs Are TTL-Voltage Compatible
• Speed of Bipolar F, AS, and S, With
Significantly Reduced Power Consumption
• Balanced Propagation Delays
• ±24-mA Output Drive Current
– Fanout to 15 F Devices
• SCR-Latchup-Resistant CMOS Process and Circuit Design
• Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015

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