CD74HC173E - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

CD74HC173E
Manufacturer

TI
ChipWorker Part#

CW6376892
Category

Flip Flop IC
Package

DIP-16
Description

TEXAS INSTRUMENTS CD74HC173E Flip-Flop, Tri State Non Inverted, Positive Edge, 74HC173, D, 17ns, 60MHz, 7.8mA, DIP
Documentation

Datasheet

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CD74HC173E Specifications

Attribute	Attribute Value

Part Number	CD74HC173E
Manufacturer	TI
ChipWorker Part#	CW6376892
Category	Flip Flop IC
Documentation	Datasheet
Mounting Style	Through Hole
Number of Pins	16 Pin
Case/Package	DIP-16
Frequency	60 MHz
Supply Voltage (DC)	2.00V (min)
Number of Outputs	4 Output
Output Current	7.8 mA
Number of Channels	4 Channel
Number of Positions	16 Position
Clock Speed	60 MHz
Number of Bits	4 Bit
Polarity	Non-Inverting
Input Capacitance	10 pF
Number of Inputs	4 Input
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-55 ℃
Supply Voltage	2V ~ 6V
Supply Voltage (Max)	6 V
Supply Voltage (Min)	2 V
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Operating Temperature	-55℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Each
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The CD74HC173E is a quad D-type Flip-flop with 3-state outputs. It is fabricated with silicon gate CMOS technology. It possesses the low power consumption of standard CMOS Integrated circuits and can operate at speeds comparable to the equivalent low power Schottky devices. The buffered outputs can drive 15 LSTTL loads. The large output drive capability and three-state feature make these parts ideally suited for interfacing with bus lines in bus oriented systems. The four D-type flip-flops operate synchronously from a common clock. The outputs are in the three-state mode when either of the two output disable pins are at the logic "1, level. The input enables allow the flip-flops to remain in their present states without having to disrupt the clock If either of the 2 input ENABLES are taken to a logic "1" level, the Q outputs are fed back to the inputs, forcing the flip-flops to remain in the same state. Reset is enabled by taking the MR input to a logic "1" level.
Gated input and output enables
Balanced propagation delay and transition times
Significant power reduction compared to LSTTL logic ICs
High noise immunity
Direct LSTTL input logic compatibility
CMOS Input compatibility
10 LSTTL Load standard outputs
15 LSTTL Load bus driver outputs
Green product and no Sb/Br

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