CD74HC237E - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

CD74HC237E
Manufacturer

TI
ChipWorker Part#

CW3327004
Category

Logic Controller, Logic IC
Package

PDIP-16
Description

TEXAS INSTRUMENTS CD74HC237E Decoder / Demultiplexer, HC Family, 8 Output, 5.2mA, 2V to 6V, DIP-16
Documentation

Datasheet

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CD74HC237E Specifications

Attribute	Attribute Value

Part Number	CD74HC237E
Manufacturer	TI
ChipWorker Part#	CW3327004
Category	Logic Controller, Logic IC
Documentation	Datasheet
Mounting Style	Through Hole
Number of Pins	16 Pin
Case/Package	PDIP-16
Supply Voltage (DC)	2.00V ~ 6.00V
Number of Outputs	8 Output
Output Voltage	2.0V ~ 6.0V
Number of Circuits	1 Circuit
Number of Positions	16 Position
Number of Bits	3 Bit
Voltage Nodes	2.00 V, 4.50 V, 6.00 V
Bandwidth	28.0 MHz
Number of Inputs	3 Input
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-55 ℃
Supply Voltage	2V ~ 6V
Supply Voltage (Max)	6 V
Supply Voltage (Min)	2 V
Input Voltage	0.5V ~ 1.5V
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Size-Length	19.3 mm
Size-Width	6.35 mm
Size-Height	4.57 mm
Operating Temperature	-55℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The CD74HC237E is a 3-to-8 high speed CMOS Decoder/Demutiplexer with address latches. It is well suited to memory address decoding or data routing applications. Both circuits feature low power consumption usually associated with CMOS circuitry, yet have speeds comparable to low power Schottky TTL logic. It three binary select inputs (A0, A1 and A2) that can be latched by an active high LE signal to isolate the outputs from select-input changes. A "Low" LE makes the output transparent to the input and the circuit functions as a one-of-eight decoder. Two Output Enable inputs (OE\1 and OE0) are provided to simplify cascading and to facilitate demultiplexing. The demultiplexing function is accomplished by using the A0, A1, A2 inputs to select the desired output and using one of the other Output Enable inputs as the data input while holding the other output enable input in its active state.
I/O Port or memory selector
Two enable inputs to simplify cascading
Balanced propagation delay and transition times
Significant power reduction compared to LSTTL logic ICs
High noise immunity
Direct LSTTL input logic compatibility
CMOS Input compatibility
10 LSTTL Load standard outputs
15 LSTTL Load bus driver outputs

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