CD74HC373E - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

CD74HC373E
Manufacturer

TI
ChipWorker Part#

CW3318490
Category

Latche IC
Package

DIP-20
Description

Latch, HC Family, 74HC373, D Type Transparent, Tri State Non Inverted, 26ns, 7.8mA, DIP
Documentation

Datasheet

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CD74HC373E Specifications

Attribute	Attribute Value

Part Number	CD74HC373E
Manufacturer	TI
ChipWorker Part#	CW3318490
Category	Latche IC
Documentation	Datasheet
Mounting Style	Through Hole
Number of Pins	20 Pin
Case/Package	DIP-20
Digital Logic Level	CMOS
Supply Voltage (DC)	5.00 V, 6.00 V (max)
Number of Outputs	8 Output
Output Current	7.8 mA
Number of Circuits	8 Circuit
Number of Channels	8 Channel
Number of Positions	20 Position
Number of Bits	8 Bit
Polarity	Non-Inverting
Number of Inputs	8 Input
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-55 ℃
Supply Voltage	2V ~ 6V
Supply Voltage (Max)	6 V
Supply Voltage (Min)	2 V
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Operating Temperature	-55℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
ECCN Code	EAR99

Product Description

The CD74HC373E is an octal CMOS Transparent Latch with 3-state outputs. This high speed latch is designed for 2 to 6V VCC operation. When the LE input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs. A buffered OE\ input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pull-up components. OE\ does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pull-up resistor.
Balanced propagation delays and transition times
Standard outputs drive up to 15 LS-TTL loads
Significant power reduction compared to LS-TTL logic ICs

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