CD74HC390E - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

CD74HC390E
Manufacturer

TI
ChipWorker Part#

CW4813033
Category

Counter, Counter IC
Package

PDIP-16
Description

TEXAS INSTRUMENTS CD74HC390E Decade Ripple Counter, HC Family, 35MHz, 2V to 6V, DIP-16
Documentation

Datasheet

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CD74HC390E Specifications

Attribute	Attribute Value

Part Number	CD74HC390E
Manufacturer	TI
ChipWorker Part#	CW4813033
Category	Counter, Counter IC
Documentation	Datasheet
Mounting Style	Through Hole
Number of Pins	16 Pin
Case/Package	PDIP-16
Supply Voltage (DC)	5.00 V, 6.00 V (max)
Number of Outputs	4 Output
Number of Channels	2 Channel
Number of Positions	16 Position
Clock Speed	35 MHz
Number of Bits	4 Bit
Number of Inputs	2 Input
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-55 ℃
Supply Voltage	2V ~ 6V
Supply Voltage (Max)	6 V
Supply Voltage (Min)	2 V
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Operating Temperature	-55℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The CD74HC390E is a high speed CMOS dual decade Ripple Counter pin compatible with low-power Schottky TTL (LSTTL). It is divided into four separately clocked sections. The counter has two divide-by-2 sections and two divide-by-5 sections. These sections are normally used in a BCD decade or bi quinary configuration, since they share a common master reset (nMR). If the two master reset inputs (1MR and 2MR) are used to simultaneously clear all 8 bits of the counter, a number of counting configurations are possible within one package. The separate clock inputs (nCP0\ and nCP1\\) of each section allow ripple counter or frequency division applications of divide-by-2, 4. 5, 10, 20, 25, 50 or 100. Each section is triggered by the high-to-low transition of the input pulses (nCP0\ and nCP1\\). For BCD decade operation, the nQ0 output is connected to the nCP1\ input of the divide-by-5 section.
Two master reset inputs to clear each decade counter individually
Balanced propagation delay and transition times
Significant power reduction compared to LSTTL logic ICs
High noise immunity
Direct LSTTL input logic compatibility
CMOS Input compatibility

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