CD74HC7046AM - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

CD74HC7046AM
Manufacturer

TI
ChipWorker Part#

CW5512296
Category

Clock Chip, Timing IC
Package

SOIC-16
Description

PLL Single 12MHz to 18MHz 16Pin SOIC Tube
Documentation

Datasheet

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CD74HC7046AM Specifications

Attribute	Attribute Value

Part Number	CD74HC7046AM
Manufacturer	TI
ChipWorker Part#	CW5512296
Category	Clock Chip, Timing IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	16 Pin
Case/Package	SOIC-16
Frequency	38 MHz
Supply Voltage (DC)	2.00V (min)
Number of Outputs	1 Output
Supply Current	8.00 µA
Number of Circuits	1 Circuit
Number of Positions	16 Position
Number of Bits	1 Bit
Voltage Nodes	6.00 V, 5.00 V, 2.00 V
Duty Cycle	50 %
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-55 ℃
Supply Voltage	2V ~ 6V
Supply Voltage (Max)	6 V
Supply Voltage (Min)	2 V
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Size-Length	9.9 mm
Size-Width	3.91 mm
Size-Height	1.58 mm
Operating Temperature	-55℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Each
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The CD74HC7046AM is a Phase-locked Loop with VCO and lock detector. High-speed silicon-gate CMOS device, specified in compliance with JEDEC Standard No. 7A, are phase-locked-loop (PLL) circuits that contain a linear voltage-controlled oscillator (VCO), two-phase comparators (PC1, PC2) and a lock detector. A signal input and a comparator input are common to each comparator. The lock detector gives a HIGH level at pin 1 (LD) when the PLL is locked. The lock detector capacitor must be connected between pin 15 (CLD) and pin 8 (Gnd). For a frequency range of 100kHz to 10MHz, the lock detector capacitor should be 1000 to 10pF respectively. The signal input can be directly coupled to large voltage signals or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers.
Excellent VCO frequency linearity
VCO-inhibit control for ON/OFF keying and for low standby power consumption
Minimal frequency drift
Zero voltage offset due to op-amp buffer
Balanced Propagation Delay and Transition Times
10 LSTTL Loads (standard outputs) and 15 LSTTL loads (bus driver outputs) fanout
NIL = 30%, NIH = 30% of VCC at VCC = 5V High noise immunity

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