CD74HC73E - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

CD74HC73E
Manufacturer

TI
ChipWorker Part#

CW2461100
Category

Flip Flop IC
Package

DIP-14
Description

TEXAS INSTRUMENTS CD74HC73E Flip-Flop, with Reset, Complementary, Negative Edge, 74HC73, JK, 13ns, 35MHz, 5.2mA, DIP
Documentation

Datasheet

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CD74HC73E Specifications

Attribute	Attribute Value

Part Number	CD74HC73E
Manufacturer	TI
ChipWorker Part#	CW2461100
Category	Flip Flop IC
Documentation	Datasheet
Mounting Style	Through Hole
Number of Pins	14 Pin
Case/Package	DIP-14
Frequency	35 MHz
Supply Voltage (DC)	2.00V (min)
Number of Outputs	1 Output
Output Current	5.2 mA
Number of Circuits	2 Circuit
Number of Channels	2 Channel
Number of Positions	14 Position
Clock Speed	60 MHz
Number of Bits	2 Bit
Polarity	Non-Inverting, Inverting
Input Capacitance	10 pF
Number of Inputs	2 Input
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-55 ℃
Supply Voltage	2V ~ 6V
Supply Voltage (Max)	6 V
Supply Voltage (Min)	2 V
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Size-Length	19.3 mm
Size-Width	6.35 mm
Size-Height	4.57 mm
Operating Temperature	-55℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The CD74HC73E is a high speed CMOS logic dual Negative-Edge-Triggered Flip-flop with J-K reset, clock inputs and Q and Q\ outputs. The CD74HCT73 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. It exhibits the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads. They change state on the negative-going transition of the clock pulse. Reset is accomplished asynchronously by a low level input. This device is functionally identical to the HC/HCT107 but differs in terminal assignment and in some parametric limits. The HCT logic family is functionally as well as pin compatible with the standard LS logic family.
Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times
Asynchronous reset
Complementary outputs
Buffered inputs
Balanced propagation delay and transition times
Significant power reduction compared to LSTTL logic ICs
±20mA DC input/output diode current
±25mA DC drain current

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