CD74HCT259E - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

CD74HCT259E
Manufacturer

TI
ChipWorker Part#

CW20688300
Category

Latche IC
Package

DIP-16
Description

TEXAS INSTRUMENTS CD74HCT259E Latch, HCT Family, 74HCT259, Addressable, Standard, 16ns, 4mA, DIP
Documentation

Datasheet

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CD74HCT259E Specifications

Attribute	Attribute Value

Part Number	CD74HCT259E
Manufacturer	TI
ChipWorker Part#	CW20688300
Category	Latche IC
Documentation	Datasheet
Mounting Style	Through Hole
Number of Pins	16 Pin
Case/Package	DIP-16
Supply Voltage (DC)	5.00 V, 5.50 V (max)
Number of Outputs	8 Output
Output Current	4 mA
Number of Positions	16 Position
Number of Bits	8 Bit
Polarity	Non-Inverting
Number of Inputs	1 Input
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-55 ℃
Supply Voltage	4.5V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	4.5 V
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Operating Temperature	-55℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The CD74HCT259E is a 8-bit CMOS Addressable Latch features the low-power consumption associated with CMOS circuitry and has speeds comparable to low-power Schottky. It latches three active modes and one RESET mode. When both the LE\ and master RESET (MR\\) inputs are low (8-line demultiplexer mode) the output of the addressed latch follows the data input and all other outputs are forced low. When both MR\ and LE\ are high (memory mode), all outputs are isolated from the data input, i.e., all latches hold the last data presented before the LE\ transition from low to high. A condition of LE\ low and MR\ high (addressable latch mode) allows the addressed latch"s output to follow the data input, all other latches are unaffected. The RESET mode (all outputs low) results when LE\ is high and MR\ is low.
Buffered inputs and outputs
Four operating modes
Balanced propagation delay and transition times
Significant power reduction compared to LSTTL logic ICs
High noise immunity
Direct LSTTL input logic compatibility
CMOS Input compatibility

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