CD74HCT4046AE - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

CD74HCT4046AE
Manufacturer

TI
ChipWorker Part#

CW22349559
Category

Clock Chip, Timing IC
Package

PDIP-16
Description

PLL, 38MHz, 4.5V to 5.5V, DIP-16
Documentation

Datasheet

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CD74HCT4046AE Specifications

Attribute	Attribute Value

Part Number	CD74HCT4046AE
Manufacturer	TI
ChipWorker Part#	CW22349559
Category	Clock Chip, Timing IC
Documentation	Datasheet
Mounting Style	Through Hole
Number of Pins	16 Pin
Case/Package	PDIP-16
Frequency	38 MHz
Supply Voltage (DC)	4.50V (min)
Supply Current	8.00 µA
Number of Circuits	1 Circuit
Number of Positions	16 Position
Number of Bits	1 Bit
Voltage Nodes	5.00 V
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-55 ℃
Supply Voltage	4.5V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	4.5 V
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Size-Width	6.35 mm
Operating Temperature	-55℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2014/12/17
ECCN Code	EAR99

Product Description

The CD74HCT4046AE is a high-speed CMOS logic Phase-locked Loop with VCO. High-speed silicon-gate CMOS device that is pin compatible with the CD4046B of the "4000B" series. They are specified in compliance with JEDEC standard number 7. The HCT4046A is phase-locked-loop circuits that contain a linear voltage-controlled oscillator (VCO) and three different phase comparators (PC1, PC2 and PC3). A signal input and a comparator input are common to each comparator. The signal input can be directly coupled to large voltage signals or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive low-pass filter, the 4046A forms a second-order loop PLL. The excellent VCO linearity is achieved by the use of linear op-amp techniques.
Excellent VCO frequency linearity
VCO-inhibit control for ON/OFF keying and for low standby power consumption
Minimal frequency drift
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
10 LSTTL Loads (standard outputs) and 15 LSTTL loads (bus driver outputs) fanout
VIL= 0.8V (maximum), VIH = 2V (minimum) Direct LSTTL input logic compatibility
Il

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