CD74HCT4094E - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

CD74HCT4094E
Manufacturer

TI
ChipWorker Part#

CW6232396
Category

Shift Register IC
Package

DIP-16
Description

Shift Register/Latch Single 8Bit Serial to Serial/Parallel 16Pin PDIP Tube
Documentation

Datasheet

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CD74HCT4094E Specifications

Attribute	Attribute Value

Part Number	CD74HCT4094E
Manufacturer	TI
ChipWorker Part#	CW6232396
Category	Shift Register IC
Documentation	Datasheet
Mounting Style	Through Hole
Number of Pins	16 Pin
Case/Package	DIP-16
Supply Voltage (DC)	5.00 V, 5.50 V (max)
Number of Outputs	10 Output
Output Current	4.00 mA
Number of Channels	1 Channel
Number of Positions	16 Position
Number of Bits	8 Bit
Number of Inputs	1 Input
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-55 ℃
Supply Voltage	4.5V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	4.5 V
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Operating Temperature	-55℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The CD74HCT4094E is a 8-stage CMOS shift-and-store Bus Register with the 3-stage outputs. It has a storage latch associated with each stage for strobing data from the serial input to parallel buffered three-state outputs. The parallel outputs may be connected directly to common bus lines. Data is shifted on positive clock transitions. The data in each shift register stage is transferred to the storage register when the Strobe input is high. Data in the storage register appears at the outputs whenever the OE signal is high. Two serial outputs are available for cascading a number of these devices. Data is available at the QS1 serial output terminal on positive clock edges to allow for high-speed operation in cascaded system in which the clock rise time is fast. The same serial information, available at the QS2 terminal on the next negative clock edge, provides a means for cascading these devices when the clock rise time is slow.
Buffered inputs
Separate serial outputs synchronous to both positive and negative clock edges for cascading
Balanced propagation delay and transition times
Significant power reduction compared to LSTTL logic ICs
High noise immunity
Direct LSTTL input logic compatibility
CMOS Input compatibility
10 LSTTL Loads standard outputs
15 LSTTL Loads bus driver outputs

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