CDC3RL02BYFPR - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

CDC3RL02BYFPR
Manufacturer

TI
ChipWorker Part#

CW9503421
Category

Clock Buffer, Driver, PLL IC
Package

DSBGA-8
Description

Clock Buffer 2Out 1IN 1:1 8Pin DSBGA T/R
Documentation

Datasheet

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CDC3RL02BYFPR Specifications

Attribute	Attribute Value

Part Number	CDC3RL02BYFPR
Manufacturer	TI
ChipWorker Part#	CW9503421
Category	Clock Buffer, Driver, PLL IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	8 Pin
Case/Package	DSBGA-8
Frequency	52 MHz
Supply Voltage (DC)	2.30V (min)
Number of Outputs	2 Output
Number of Circuits	1 Circuit
Number of Positions	8 Position
Duty Cycle	55 %
Maximum Duty Cycle	55 %
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	2.3V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	2.3 V
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Size-Length	1.59 mm
Size-Width	0.79 mm
Size-Height	0.5 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The CDC3RL02 is a two-channel clock fan-out buffer and is ideal for use in portable end-equipment, such as mobile phones, that require clock buffering with minimal additive phase noise and fan-out capabilities. It buffers a single master clock, such as a temperature compensated crystal oscillator (TCXO) to multiple peripherals. The device has two clock request inputs (CLK_REQ1 and CLK_REQ2), each of which enable a single clock output.
The CDC3RL02 accepts square or sine waves at the master clock input (MCLK_IN), eliminating the need for an AC coupling capacitor. The smallest acceptable sine wave is a 0.3-V signal (peak-to-peak). CDC3RL02 has been designed to offer minimal channel-to-channel skew, additive output jitter, and additive phase noise. The adaptive clock output buffers offer controlled slew-rate over a wide capacitive loading range which minimizes EMI emissions, maintains signal integrity, and minimizes ringing caused by signal reflections on the clock distribution lines.
The CDC3RL02 has an integrated Low-Drop-Out (LDO) voltage regulator which accepts input voltages from 2.3 V to 5.5 V and outputs 1.8 V, 50 mA. This 1.8-V supply is externally available to provide regulated power to peripheral devices such as a TCXO.
The CDC3RL02 is offered in a 0.4-mm pitch wafer-level chip-scale (WCSP) package (0.8 mm × 1.6 mm) and is optimized for very low standby current consumption.

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