CDCE62005RGZT - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

CDCE62005RGZT
Manufacturer

TI
ChipWorker Part#

CW3543773
Category

Clock Chip, Timing IC
Package

VQFN-48
Description

5/10Outputs Clock Generator/Jitter Cleaner with Integrated Dual VCO 48-VQFN -40℃ to 85℃
Documentation

Datasheet

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CDCE62005RGZT Specifications

Attribute	Attribute Value

Part Number	CDCE62005RGZT
Manufacturer	TI
ChipWorker Part#	CW3543773
Category	Clock Chip, Timing IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	48 Pin
Case/Package	VQFN-48
Frequency	1.175 GHz
Supply Voltage (DC)	3.30 V
Number of Outputs	5 Output
Supply Current	20.0 mA
Number of Circuits	1 Circuit
Number of Positions	48 Position
Input Current	20.0 mA
Duty Cycle	55% (Max)
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	3V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	3 V
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Size-Length	7 mm
Size-Width	7 mm
Size-Height	0.9 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
Mil-Spec	Yes
ECCN Code	EAR99

Product Description

The CDCE62005RGZT is a high-performance Clock Generator and Distributor features low output jitter, a high degree of configurability via a SPI interface and programmable start up modes determined by on-chip EEPROM. Specifically tailored for clocking data converters and high-speed digital signals, the CDCE62005 achieves jitter performance well under 1ps RMS (10kHz to 20MHz integration bandwidth). It incorporates a synthesizer block with partially integrated loop filter, a clock distribution block including programmable output formats and an input block featuring an innovative smart multiplexer. The clock distribution block includes five individually programmable outputs that can be configured to provide different combinations of output formats (LVPECL, LVDS, LVCMOS). Each output can also be programmed to unique output frequency (up to 1.5GHz) and skew relationship via a programmable delay block. If all outputs are configured in single-ended mode (for example, LVCMOS).
Integrated EEPROM determines device configuration at power-up
Smart input multiplexer automatically switches between one of three reference inputs
Independent coarse skew control on all outputs
LVPECL, LVDS, LVCMOS and special high swing output modes
Unique Dual-VCO architecture supports a wide tuning range
2.6ps RMS Typical low noise jitter cleaner
550fs RMS Low noise clock generator
Green product and no Sb/Br
Device has limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

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