CDCE72010RGCT - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

CDCE72010RGCT
Manufacturer

TI
ChipWorker Part#

CW19051431
Category

Clock Generator IC
Package

VQFN-64
Description

Clock Generator 500MHz Input 1500MHz Output 64Pin VQFN EP T/R
Documentation

Datasheet

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CDCE72010RGCT Specifications

Attribute	Attribute Value

Part Number	CDCE72010RGCT
Manufacturer	TI
ChipWorker Part#	CW19051431
Category	Clock Generator IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	64 Pin
Case/Package	VQFN-64
Frequency	1.5 GHz
Supply Voltage (DC)	3.30 V
Number of Outputs	20 Output
Supply Current	20.0 mA
Number of Circuits	1 Circuit
Number of Positions	64 Position
Power Dissipation	0.53 W
Duty Cycle	60% (Max)
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Power Dissipation (Max)	530 mW
Supply Voltage	3V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	3 V
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Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The CDCE72010RGCT is a high-performance low phase noise/low skew Clock Synchronizer that synchronizes a VCXO (Voltage Controlled Crystal Oscillator) or VCO (Voltage Controlled Oscillator) frequency to one of two reference clocks. The clock path is fully programmable providing the user with a high degree of flexibility. The PLL loop bandwidth and damping factor can be adjusted to meet different system requirements. The CDCE72010 can lock to one of two reference clock inputs (PRI_REF and SEC_REF) and supports frequency hold-over mode for fail-safe and system redundancy. The outputs of the CDCE72010 are user definable and can be any combination of up to 10 LVPECL/LVDS outputs or up to 20 LVCMOS outputs. The built-in synchronization latches ensure that all outputs are synchronized for very low output skew. All device settings, including output signalling, divider value selection, input selection and many more, are programmable with the SPI (4-wire Serial Peripheral Interface).
Two reference clock inputs (primary and secondary clock) for redundancy
Support with manual or automatic selection
SPI controllable device setting
Individual output enables control via SPI interface
Optional configuration pins to select between two default settings stored in EEPROM
Efficient jitter cleaning from low PLL loop bandwidth
Very low phase noise PLL core
Programmable phase offset (input reference to outputs)
Wide charge-pump current range from 200µA to 3mA
SERDES startup mode (depending on VCXO range)

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