CDCE906PWG4 - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

CDCE906PWG4
Manufacturer

TI
ChipWorker Part#

CW69823571
Category

Clock Chip, Timing IC
Package

TSSOP-20
Description

Clock Generator 1MHz to 167MHz Input 167MHz Output 20Pin TSSOP Tube
Documentation

Datasheet

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CDCE906PWG4 Specifications

Attribute	Attribute Value

Part Number	CDCE906PWG4
Manufacturer	TI
ChipWorker Part#	CW69823571
Category	Clock Chip, Timing IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	20 Pin
Case/Package	TSSOP-20
Frequency	167 MHz
Supply Voltage (DC)	3.30 V
Number of Outputs	6 Output
Supply Current	115 mA
Number of Circuits	1 Circuit
Number of Positions	20 Position
Duty Cycle	60% (Max)
Operating Temperature (Max)	70 ℃
Operating Temperature (Min)	0 ℃
Supply Voltage	3V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	3 V
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Size-Width	4.4 mm
Operating Temperature	0℃ ~ 70℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2014/12/17

Product Description

The CDCE906PWG4 is a 3-PLL Programmable Clock Synthesizer/Multiplier/Divider despites its small physical outlines, it is very flexible. It has the capability to produce an almost independent output frequency from a given input frequency. The input frequency can be derived from a LVCMOS, differential input clock or a single crystal. The appropriate input waveform can be selected via the SMBus data interface controller. To achieve an independent output frequency the reference divider M and the feedback divider N for each PLL can be set to values from 1 up to 511 for the M-divider and from 1 up to 4095 for the N-divider. The PLL-VCO (voltage controlled oscillator) frequency than is routed to the free programmable output switching matrix to any of the six outputs. The switching matrix includes an additional 7-bit post-divider (1-to-127) and an inverting logic for each output. The deep M/N divider ratio allows the generation of zero ppm clocks from any reference input frequency (27MHz).
User programmable PLL frequencies
EEPROM Programming without the need to apply high programming voltage
Easy in-circuit programming via SMBus data interface
Wide PLL divider ratio allows 0ppm output clock error
Clock inputs accept a crystal or a single-ended LVCMOS or a differential input signal
LVCMOS Outputs can be programmed for complementary signals
PLL loop filter components integrated
Programmable down spread SSC modulation
Programmable output slew-rate control (SRC) for lowering system EMI
Development and programming kit for easy PLL design and programming
Green product and no Sb/Br

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