CDCE949QPWRQ1 - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

CDCE949QPWRQ1
Manufacturer

TI
ChipWorker Part#

CW8161503
Category

Clock Generator IC
Package

TSSOP-24
Description

Clock Generator 8MHz to 160MHz Input 230MHz Output Automotive 24Pin TSSOP T/R
Documentation

Datasheet

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CDCE949QPWRQ1 Specifications

Attribute	Attribute Value

Part Number	CDCE949QPWRQ1
Manufacturer	TI
ChipWorker Part#	CW8161503
Category	Clock Generator IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	24 Pin
Case/Package	TSSOP-24
Supply Voltage (DC)	1.80 V
Number of Outputs	9 Output
Supply Current	38 mA
Number of Circuits	1 Circuit
Duty Cycle	60% (Max)
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	1.7V ~ 1.9V
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Operating Temperature	-40℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free

Product Description

The CDCE949 is a modular PLL-based low-cost high-performance programmable clock synthesizer, multiplier, and divider. It generates up to 9 output clocks from a single input frequency. Each output can be programmed in-system for any clock frequency up to 230 MHz, using up to four independent configurable PLLs.
The CDCE949 has separate output supply pins, VDDOUT, of 2.5 V to 3.3 V.
The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 to 20 pF. Additionally, an on-chip VCXO is selectable, allowing synchronization of the output frequency to an external control signal, that is, a PWM signal.
The deep M/N divider ratio allows the generation of zero-ppm audio/video, networking (WLAN, BlueTooth™, Ethernet, GPS) or Interface (USB, IEEE1394, Memory Stick) clocks from a reference input frequency, such as 27 MHz.
All PLLs support SSC (Spread-Spectrum Clocking). SSC can be Center-Spread or Down-Spread clocking. This is a common technique to reduce electro-magnetic interference (EMI).
Based on the PLL frequency and the divider settings, the internal loop-filter components are automatically adjusted to achieve high stability, and to optimize the jitter-transfer characteristics of each PLL.
The device supports non-volatile EEPROM programming for easy customization of the device to the application. It is preset to a factory-default configuration (see the _Default device Configuration_ section). It can be reprogrammed to a different application configuration before PCB assembly, or reprogrammed by in-system programming. All device settings are programmable through the SDA/SCL bus, a 2-wire serial interface.
Three programmable control inputs, S0, S1 and S2, can be used to control various aspects of operation including frequency selection, changing the SSC parameters to lower EMI, PLL bypass, power down, and choosing between low level or 3-state for the output-disable function.
The CDCE949 operates in a 1.8 V environment. It operates within a temprateure range of –40°C to 125°C.

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