CDCLVD1204RGTT - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

CDCLVD1204RGTT
Manufacturer

TI
ChipWorker Part#

CW2016100
Category

Clock Buffer, Driver, PLL IC
Package

QFN-16
Description

Clock Multiplexer 4Out 2IN 1:4 16Pin VQFN EP T/R
Documentation

Datasheet

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CDCLVD1204RGTT Specifications

Attribute	Attribute Value

Part Number	CDCLVD1204RGTT
Manufacturer	TI
ChipWorker Part#	CW2016100
Category	Clock Buffer, Driver, PLL IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	16 Pin
Case/Package	QFN-16
Frequency	800 MHz
Supply Voltage (DC)	2.50 V
Number of Outputs	4 Output
Supply Current	60.0 mA
Number of Circuits	1 Circuit
Number of Positions	16 Position
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	2.375V ~ 2.625V
Supply Voltage (Max)	2.625 V
Supply Voltage (Min)	2.375 V
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Size-Length	3.15 mm
Size-Width	3.15 mm
Size-Height	0.95 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The CDCLVD1204RGTT is a Clock Buffer distributes one of two selectable clock inputs, (IN0, IN1), to 4 pairs of differential LVDS clock outputs (OUT0, OUT3) with minimum skew for clock distribution. It can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL or LVCMOS. It is specifically designed for driving 50R transmission lines. In case of driving the inputs in single ended mode, the appropriate bias voltage (VAC_REF) should be applied to the unused negative input pin. The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open it disables the outputs (static). The part supports a fail-safe function. The device incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.
2:4 Differential buffer
Universal inputs accept LVDS, LVPECL and LVCMOS
Selectable clock inputs through control pin
4 LVDS outputs, ANSI EAI/TIA-644A standard compatible
<300fs RMS in 10kHz to 20MHz low additive jitter
20ps Maximum low output skew
Green product and no Sb/Br
Device has limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

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