CDCLVP1102RGTT - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

CDCLVP1102RGTT
Manufacturer

TI
ChipWorker Part#

CW1876108
Category

Clock Buffer, Driver, PLL IC
Package

QFN-16
Description

Clock Fanout Buffer 2Out 1IN 1:2 16Pin VQFN EP T/R
Documentation

Datasheet

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CDCLVP1102RGTT Specifications

Attribute	Attribute Value

Part Number	CDCLVP1102RGTT
Manufacturer	TI
ChipWorker Part#	CW1876108
Category	Clock Buffer, Driver, PLL IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	16 Pin
Case/Package	QFN-16
Frequency	2 GHz
Supply Voltage (DC)	2.38V ~ 3.60V
Number of Outputs	2 Output
Supply Current	100 mA
Number of Circuits	1 Circuit
Number of Positions	16 Position
Input Current	33.0 mA
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	2.375V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	2.375 V
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Size-Length	3.15 mm
Size-Width	3.15 mm
Size-Height	0.95 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The CDCLVP1102RGTT is a highly versatile low additive Jitter Buffer can generate two copies of LVPECL clock outputs from one LVPECL, LVDS or LVCMOS input for a variety of communication applications. It has a maximum clock frequency up to 2GHz. The overall additive jitter performance is less than 0.1ps, RMS from 10kHz to 20MHz and overall output skew is as low as 10ps, making the device a perfect choice for use in demanding applications. The CDCLVP1102 clock buffer distributes a single clock input (IN) to two pairs of differential LVPECL clock outputs (OUT0, OUT1) with minimum skew for clock distribution. The inputs can be LVPECL, LVDS or LVCMOS/LVTTL. The CDCLVP1102 is specifically designed for driving 50R transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) should be applied to the unused negative input pin. However, for high-speed performance up to 2GHz, differential mode is strongly recommended.
1:2 Differential buffer
Single clock input
Universal Inputs can accept LVPECL, LVDS and LVCMOS/LVTTL
Two LVPECL outputs
2GHz Maximum clock frequency
33mA Maximum core current consumption
<100fs Very low additive jitter
10ps Maximum output skew
Green product and no Sb/Br
Device has limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

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