CDCLVP1208RHDT - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

CDCLVP1208RHDT
Manufacturer

TI
ChipWorker Part#

CW3044800
Category

Clock Buffer, Driver, PLL IC
Package

VQFN-28
Description

Clock Multiplexer 8Out 2IN 1:8 28Pin VQFN EP T/R
Documentation

Datasheet

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CDCLVP1208RHDT Specifications

Attribute	Attribute Value

Part Number	CDCLVP1208RHDT
Manufacturer	TI
ChipWorker Part#	CW3044800
Category	Clock Buffer, Driver, PLL IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	28 Pin
Case/Package	VQFN-28
Frequency	2 GHz
Supply Voltage (DC)	2.38V ~ 3.60V
Number of Outputs	8 Output
Supply Current	73.0 mA
Number of Circuits	1 Circuit
Number of Positions	28 Position
Input Current	73.0 mA
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	2.375V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	2.375 V
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Size-Length	5.15 mm
Size-Width	5.15 mm
Size-Height	0.95 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The CDCLVP1208RHDT is a highly versatile low additive Jitter Buffer can generate eight copies of LVPECL clock outputs from one of two selectable LVPECL, LVDS or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2GHz. The CDCLVP1208 features an on-chip multiplexer (MUX) for selecting one of two inputs that can be easily configured solely through a control terminal. The overall additive jitter performance is less than 0.1ps, RMS from 10kHz to 20MHz and overall output skew is as low as 20ps, making the device a perfect choice for use in demanding applications. The CDCLVP1208 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to eight pairs of differential LVPECL clock outputs (OUT0, OUT7) with minimum skew for clock distribution. The CDCLVP1208 can accept two clock sources into an input multiplexer. The inputs can be LVPECL, LVDS or LVCMOS/LVTTL.
2:8 Differential buffer
Selectable clock inputs through control terminal
Universal Inputs can accept LVPECL, LVDS and LVCMOS/LVTTL
Eight LVPECL outputs
2GHz Maximum clock frequency
73mA Maximum core current consumption
<100fs Very low additive jitter
20ps Maximum output skew
Green product and no Sb/Br
Device has limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

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