CDCM7005RGZT - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

CDCM7005RGZT
Manufacturer

TI
ChipWorker Part#

CW19050004
Category

Clock Generator IC
Package

VQFN-48
Description

Clock Generator 0MHz to 2.2GHz Input 1500MHz Output 48Pin VQFN EP T/R
Documentation

Datasheet

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CDCM7005RGZT Specifications

Attribute	Attribute Value

Part Number	CDCM7005RGZT
Manufacturer	TI
ChipWorker Part#	CW19050004
Category	Clock Generator IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	48 Pin
Case/Package	VQFN-48
Frequency	200 MHz
Supply Voltage (DC)	3.30 V
Number of Outputs	10 Output
Supply Current	210 mA
Number of Circuits	1 Circuit
Number of Positions	48 Position
Duty Cycle	51% (Max)
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	3V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	3 V
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Size-Length	7 mm
Size-Width	7 mm
Size-Height	0.9 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The CDCM7005RGZT is a high-performance low phase noise/low skew Clock Synchronizer that synchronizes a VCXO (voltage controlled crystal oscillator) or VCO (voltage controlled oscillator) frequency to one of the two reference clocks. The programmable pre-divider M and the feedback-dividers N and P give a high flexibility to the frequency ratio of the reference clock to VC(X)O VC(X)O_IN clock operates up to 2.2GHz. Through the selection of external VC(X)O and loop filter components, the PLL loop bandwidth and damping factor can be adjust to meet different system requirements. The CDCM7005 can lock to one of two reference clock inputs (PRI_REF and SEC_REF), supports frequency hold-over mode and fast-frequency-locking for fail-safe and increased system redundancy. The output of the CDCM7005 is user definable and can be any combination of up to five LVPECL outputs or up to 10 LVCMOS outputs. The built in synchronization latches ensure that all outputs are synchronized for low output skew.
VCXO_IN Clock is synchronized to one of the two reference clocks
Efficient jitter cleaning from low PLL loop bandwidth
Low phase noise PLL core
Programmable phase offset (PRI_REF and SEC_REF to outputs)
Wide charge pump current range from 200µA to 3mA
Frequency hold-over mode improves fail-safe operation
SPI controllable device setting

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