CDCVF2505D - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

CDCVF2505D
Manufacturer

TI
ChipWorker Part#

CW21382139
Category

Clock Chip, Timing IC
Package

SOIC-8
Description

Zero Delay PLL Clock Driver Single 24MHz to 200MHz 8Pin SOIC Tube
Documentation

Datasheet

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CDCVF2505D Specifications

Attribute	Attribute Value

Part Number	CDCVF2505D
Manufacturer	TI
ChipWorker Part#	CW21382139
Category	Clock Chip, Timing IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	8 Pin
Case/Package	SOIC-8
Frequency	200 MHz
Supply Voltage (DC)	3.30 V
Number of Outputs	4 Output
Supply Current	5.00 µA
Number of Circuits	1 Circuit
Output Current Drive	12.0 mA
Number of Inputs	1 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	3V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	3 V
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Size-Length	4.9 mm
Size-Width	3.91 mm
Size-Height	1.58 mm
Weight	0.0012142668548 kg
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99
HK STC License	NLR

Product Description

The CDCVF2505 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. This device uses a PLL to precisely align the output clocks (1Y[0-3] and CLKOUT) to the input clock signal (CLKIN) in both frequency and phase. The CDCVF2505 operates at 3.3 V and also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of five outputs provides low-skew, low-jitter copies of CLKIN. Output duty cycles are adjusted to 50 percent, independent of duty cycle at CLKIN. The device automatically goes into power-down mode when no input signal is applied to CLKIN.
The loop filter for the PLLs is included on-chip. This minimizes the component count, space, and cost.
The CDCVF2505 is characterized for operation from –40°C to 85°C.
Because it is based on the PLL circuitry, the CDCVF2505 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization is required following power up and application of a fixed-frequency, fixed-phase signal at CLKIN, and following any changes to the PLL reference.

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