CDCVF2505PWR - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

CDCVF2505PWR
Manufacturer

TI
ChipWorker Part#

CW3647496
Category

Clock Chip, Timing IC
Package

TSSOP-8
Description

Zero Delay PLL Clock Driver Single 24MHz to 200MHz 8Pin TSSOP T/R
Documentation

Datasheet

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CDCVF2505PWR Specifications

Attribute	Attribute Value

Part Number	CDCVF2505PWR
Manufacturer	TI
ChipWorker Part#	CW3647496
Category	Clock Chip, Timing IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	8 Pin
Case/Package	TSSOP-8
Frequency	200 MHz
Supply Voltage (DC)	3.30 V
Number of Outputs	5 Output
Supply Current	5.00 µA
Number of Circuits	1 Circuit
Number of Positions	8 Position
Output Current Drive	12.0 mA
Number of Inputs	1 Input
Maximum Duty Cycle	60 %
Fall Time (Max)	2 ns
Fall Time (Max)	2 ns
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	3V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	3 V
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Size-Length	3 mm
Size-Width	4.4 mm
Size-Height	1.15 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance Edition	2015/06/15

Product Description

The CDCVF2505PWR is a high-performance phase-lock loop (PLL) Clock Driver uses a PLL to precisely align, in both frequency and phase, the output clocks (1Y(0-3) and CLKOUT) to the input clock signal (CLKIN). The CDCVF2505 operates at 3.3V. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads. One bank of five outputs provides low-skew, low-jitter copies of CLKIN. Output duty cycles are adjusted to 50 per cent, independent of duty cycle at CLKIN. The device automatically goes in power-down mode when no input signal is applied to CLKIN. Unlike many products containing PLLs, the CDCVF2505 does not require an external RC network. The loop filter for the PLLs is included on-chip, minimizing component count and space. Because it is based on the PLL circuitry, the CDCVF2505 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal.
Phase-lock loop clock driver for synchronous DRAM and general-purpose applications
Spread spectrum clock compatible
Distributes one clock input to one bank of five outputs
Three-states outputs when there is no input clock
Internal feedback loop is used to synchronize the outputs to the input clock
Integrated RC PLL loop filter eliminates the need for external components
Green product and no Sb/Br

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